Package including a plurality of stacked semiconductor devices, an interposer and interface connections
A system can include a first semiconductor device, a second semiconductor device, and a first semiconductor memory device. The first semiconductor device can include a first capacitor having first and second capacitor nodes that each include at least one essentially vertically formed conductive portion in a substrate. The first capacitor node can be electrically connected to a first terminal, which is electrically connected to receive a power supply potential from a power supply terminal. The second semiconductor device can receive the power supply potential from the power supply terminal. At least one conductive data path can be coupled between the first semiconductor memory device and the second semiconductor device. The first capacitor node includes at least one essentially vertically formed conductive portion disposed in the substrate of the first semiconductor device and through at least half of a vertical thickness of the first semiconductor device.
1. A system, comprising:
a first semiconductor device, including a first capacitor, the first capacitor including a first capacitor node and a second capacitor node, the first and second capacitor nodes each include at least one essentially vertically formed conductive portion in a substrate of the first semiconductor device that are separated from one another by at least one capacitor dielectric and providing a substantial portion of a first capacitance value of the first capacitor, the first capacitor node is electrically connected to a first terminal of the first capacitor, the first terminal of the first capacitor electrically connected to receive a power supply potential from a power supply terminal;
a second semiconductor device electrically connected to receive the power supply potential from the power supply terminal;
a first semiconductor memory device; and
at least one conductive data path coupled between the first semiconductor memory device and the second semiconductor device, wherein;
the at least one essentially vertically formed conductive portion comprises polysilicon and the first capacitor node includes at least one essentially vertically formed conductive portion disposed in the substrate of the first semiconductor device and through at least half of a vertical thickness of the first semiconductor device.
2. The system of claim 1 , wherein:
the first semiconductor device is disposed between the second semiconductor device and the first semiconductor memory device.
3. The system of claim 2 , wherein:
the second semiconductor device includes a first voltage generator coupled to receive the power supply potential from the power supply terminal, the first voltage generator provides a first voltage generator output potential at an output terminal.
4. The system of claim 3 , further including:
the first voltage generator output potential is a reference voltage provided to an input buffer on the second semiconductor device.
5. The system of claim 3 , wherein:
the first voltage generator output potential is a power supply voltage for internal circuits formed on the second semiconductor device.
6. The system of claim 2 , further including:
a second semiconductor memory device, the first semiconductor memory device is disposed between the second semiconductor memory device and the second semiconductor device.
7. The system of claim 2 , further including:
a third semiconductor device, including a second capacitor, the second capacitor including a first capacitor node and a second capacitor node, the first and second capacitor nodes each include at least one essentially vertically formed conductive portion in a substrate of the third semiconductor device that are separated by at least one capacitor dielectric and providing a substantial portion of a first capacitance value of the second capacitor, the first capacitor node of the second capacitor is electrically connected to a first terminal of the second capacitor, the first terminal of the second capacitor connected to receive the power supply potential from the power supply terminal.
8. The system of claim 7 , further including:
the third semiconductor device is disposed between the second semiconductor device and the first semiconductor memory device.
9. The system of claim 2 , wherein the first semiconductor memory device is a dynamic random access memory device.
10. The system of claim 1 , wherein:
the second semiconductor device is disposed between the first semiconductor device and the first semiconductor memory device.
11. The system of claim 10 , wherein:
the second semiconductor device includes a first voltage generator coupled to receive the power supply potential from the power supply terminal, the first voltage generator provides a first voltage generator output potential at an output terminal.
12. The system of claim 11 , further including:
the first voltage generator output potential is a reference voltage provided to an input buffer on the second semiconductor device.
13. The system of claim 11 , wherein:
the first voltage generator output potential is a power supply voltage for internal circuits formed on the second semiconductor device.
14. The system of claim 10 , further including:
a second semiconductor memory device, the first semiconductor memory device is disposed between the second semiconductor memory device and the second semiconductor device.
15. The system of claim 10 , further including:
a third semiconductor device, including a second capacitor, the second capacitor including a first capacitor node and a second capacitor node, the first and second capacitor nodes each include at least one essentially vertically formed conductive portion in a substrate of the third semiconductor device that are separated from one another by at least one capacitor dielectric and providing a substantial portion of a first capacitance value of the second capacitor, the first capacitor node of the second capacitor is electrically connected to a first terminal of the second capacitor, the first terminal of the second capacitor connected to receive the power supply potential from the power supply terminal.
16. The system of claim 15 , further including:
the second semiconductor device is disposed between the third semiconductor device and the first semiconductor memory device.
17. The system of claim 10 , wherein the first semiconductor memory device is a dynamic random access memory device.
18. The system of claim 1 , wherein:
the second capacitor node includes at least one essentially vertically formed conductive portion disposed in the substrate of the first semiconductor device and through at least half of a vertical thickness of the first semiconductor device.
19. The system of claim 18 , wherein the first or second conductive layer has an annular shape in a horizontal direction.
20. The system of claim 1 , wherein
the second semiconductor device includes an active mode of operation; and
the first capacitor is configured to provide the power supply potential that is substantially stable when the second semiconductor device is in the active mode of operation.