Package including a plurality of stacked semiconductor devices, an interposer and interface connections
A system can include a first semiconductor device including a first capacitor with a first terminal coupled to receive a power supply potential; and a second semiconductor device including a first voltage generator coupled to the first terminal of the first capacitor, the first voltage generator provides a first voltage generator output potential at an output terminal. The first capacitor can include a first capacitor node and a second capacitor node, the first capacitor node and the second capacitor node each include at least one substantially vertically formed conductive portion in a substrate of the first semiconductor device that are separated from one another by at least one capacitor dielectric, the first capacitor node is electrically connected to the first terminal of the first capacitor.
1. A system, comprising:
a first semiconductor device including a first capacitor, the first capacitor including a first terminal coupled to receive a power supply potential; and
a second semiconductor device including a first voltage generator coupled to the first terminal of the first capacitor, the first voltage generator provides a first voltage generator output potential at an output terminal; wherein
the first capacitor includes a first capacitor node and a second capacitor node, the first capacitor node and the second capacitor node each include at least one substantially vertically formed conductive portion in a substrate of the first semiconductor device that are separated from one another by at least one capacitor dielectric, the first capacitor node is electrically connected to the first terminal of the first capacitor.
2. The system of claim 1 , further including:
a third semiconductor device including a second capacitor, the second capacitor including a first terminal coupled to receive the power supply potential; wherein
the second capacitor includes a first capacitor node and a second capacitor node, the first capacitor node and the second capacitor node each include substantially vertically formed conductive portions in a substrate of the third semiconductor device that are separated from one another by at least one capacitor dielectric, the first capacitor node of the second capacitor is electrically connected to the first terminal of the second capacitor.
3. The system of claim 2 , further including:
a fourth semiconductor device including a third capacitor, the third capacitor including a first terminal coupled to receive the power supply potential; wherein
the third capacitor includes a first capacitor node and a second capacitor node, the first capacitor node and the second capacitor node each include substantially vertically formed conductive portions in a substrate of the fourth semiconductor device that are separated from one another by at least one capacitor dielectric, the first capacitor node of the third capacitor is electrically connected to the first terminal of the third capacitor.
4. The system of claim 1 , wherein:
the at least one substantially vertically formed conductive portion of the first and second capacitor nodes includes
a first conductive material vertically disposed in the substrate of the first semiconductor device,
a second conductive material vertically disposed in the substrate of the first semiconductor device, and
the at least one dielectric formed between the first and second conductive materials.
5. The system of claim 4 , wherein the first or second conductive material is selected from the group of: polysilicon, copper, aluminum, cobalt, nickel, and titanium.
6. The system of claim 4 , wherein the first or second conductive material has an annular shape.
7. The system of claim 1 , wherein the second capacitor node is electrically connected to a reference potential.
8. The system of claim 1 , wherein the at least one dielectric is selected from the group of: silicon dioxide, nitride, zirconium oxide, aluminum oxide, and hafnium oxide.
9. The system of claim 1 , further including:
the first semiconductor device is disposed in a first direction from the second semiconductor device;
a first semiconductor memory device is disposed in a second direction, opposite to the first direction, from the second semiconductor device; and
at least one conductive data path coupled between the first semiconductor memory device and the second semiconductor device.
10. The system of claim 9 , further including a second semiconductor memory device is disposed in the second direction from the second semiconductor device.
11. The system of claim 9 , wherein the first semiconductor memory device is coupled to receive the power supply potential.
12. The system of claim 9 , wherein the first semiconductor memory device is a dynamic random access memory (DRAM) device.
13. The system of claim 9 , wherein the first semiconductor memory device includes a second voltage generator coupled to the first terminal of the first capacitor, the second voltage generator provides a second voltage generator output potential at a second output terminal.
14. The system of claim 13 , wherein the second voltage generator output is selected from the group of: a reference voltage provided to an input buffer on the first semiconductor memory device, a power supply voltage for the first semiconductor memory device, and a bit line reference voltage for the first semiconductor memory device.
15. The system of claim 1 , wherein the first voltage generator output potential is a reference voltage provided to an input buffer on the second semiconductor device.
16. The system of claim 1 , wherein the first voltage generator output potential is a power supply voltage for internal circuits formed on the second semiconductor device.
17. The system of claim 1 , wherein the first voltage generator output potential is a boosted power supply voltage.
18. The system of claim 1 , further including an interface connection coupled between the second semiconductor device and the first terminal of the first capacitor.
19. The system of claim 18 , wherein the interface connection comprises a material selected from the group of: solder or copper.
20. The system of claim 1 , wherein
the second semiconductor device includes an active mode of operation; and
the first capacitor is configured to provide a power supply potential that is substantially stable when the second semiconductor device is in the active mode of operation.
21. The system of claim 1 , further including:
a first semiconductor memory device
the first semiconductor device is disposed between the first semiconductor memory device and the second semiconductor device; and
at least one conductive data path coupled between the first semiconductor memory device and the second semiconductor device.
22. The system of claim 21 , further including a second semiconductor memory device, the first semiconductor memory device is disposed between the second semiconductor memory device and the second semiconductor device.