Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture

1. A package, comprising:

a first semiconductor device and a second semiconductor device stacked in a first direction;

the first semiconductor device including

a first circuit formed on the first semiconductor device, the first circuit provides a first potential greater than a ground potential at a first circuit output;

a second circuit formed on the first semiconductor device and coupled to receive the first circuit output;

the second semiconductor device including

a first through via providing a first electrical connection in the first direction between a first side and a second side opposite the first side of the second semiconductor device; and

a third circuit formed on the second side of the second semiconductor device wherein

the first circuit output is electrically connected to the first through via at the first side of the second semiconductor device and the third circuit is electrically connected to the first through via at the second side of the second semiconductor device to receive the first potential.

2. The package of claim 1 , wherein:

the second semiconductor device includes a fourth circuit having a second circuit output electrically connected to the first through via at the second side of the second semiconductor device, the first circuit and the second circuit provide the first potential.

3. The package of claim 1 , wherein:

the first potential is a bit line reference potential.

4. The package of claim 3 , wherein:

the first semiconductor device is a semiconductor memory device and the second semiconductor device is a semiconductor memory device;

the second circuit is a first bit line precharge circuit coupled to receive the bit line reference potential; and

the third circuit is a second bit line precharge circuit coupled to receive the bit line reference potential.

5. The package of claim 1 , wherein:

the first semiconductor device includes an internal power supply generator circuit electrically connected to receive an external power supply potential and provide an internal power supply potential and the first circuit is coupled to receive the internal power supply potential.

6. The package of claim 1 , wherein:

the second circuit is a first input buffer electrically connected to receive the first potential.

7. The package of claim 6 , wherein:

the third circuit is a second input buffer electrically connected to receive the first potential.

8. The package of claim 6 , wherein:

the first semiconductor device includes an internal power supply generator circuit electrically connected to receive an external power supply potential and provide an internal power supply potential and the first circuit is electrically connected to receive the internal power supply potential.

9. The package of claim 1 , wherein:

the first potential is an internal power supply potential; and

the first semiconductor device includes internal circuits that are electrically connected to receive and are powered by the internal power supply potential.

10. The package of claim 9 , further including:

an external connection coupled to receive an external power supply potential, the external power supply potential is generated externally to the package wherein

the first circuit is electrically connected to receive the external power supply potential.

11. The package of claim 1 , wherein:

the first potential is a boosted power supply potential.

12. The package of claim 11 , wherein:

the first semiconductor device is a semiconductor memory device and the second semiconductor device is a semiconductor memory device;

the second circuit is a first word line driver circuit electrically connected to receive the boosted power supply potential; and

the third circuit is a second word line driver circuit electrically connected to receive the boosted power supply potential.

13. The package of claim 12 , wherein:

the first semiconductor device is a dynamic random access memory (DRAM) device and the second semiconductor device is a DRAM device.

14. The package of claim 1 , wherein:

the second semiconductor device includes a second through via providing a second electrical connection in the first direction between the first side and the second side opposite the first side of the second semiconductor device; and

the first through via has a first capacitance value and the second through via has a second capacitance value that is less than the first capacitance value.

15. The package of claim 14 , wherein:

the first capacitance value is substantially greater than the second capacitance value.

16. The package of claim 15 , wherein:

the first capacitance value is at least 10 times greater than the second capacitance value.

17. The package of claim 1 , wherein:

the first through via including

a first conductive material providing the electrical connection between the first surface and the second surface of the second semiconductor device; and

a second conductive material surrounding at least a portion of the first conductive material and separated from the first conductive material by a first dielectric layer.

18. The package of claim 17 , further including:

the second conductive material is electrically connected to a second potential.

19. The package of claim 18 , wherein:

the second potential is the ground potential.

20. The package of claim 1 , wherein:

the first potential remains substantially stable while the first semiconductor device is in an active mode of operation.