Linearity and lateral isolation in a BiCMOS process through counter-doping of epitaxial silicon region
Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation and optional deep trench isolation regions are formed through the counter-doped second region, providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.
1. A method comprising:
growing an epitaxial layer over a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type and the epitaxial layer has a second conductivity type, opposite the first conductivity type;
forming a mask over the epitaxial layer, wherein the mask covers a first region of the epitaxial layer and exposes a second region of the epitaxial layer;
implanting a dopant having the first conductivity type through the mask into the second region of the epitaxial layer, whereby the second region of the epitaxial layer becomes counter-doped to the first conductivity type;
forming one or more shallow trench isolation regions in the counter-doped second region of the epitaxial layer, wherein portions of the counter-doped second region of the epitaxial layer are exposed through the one or more shallow trench isolation regions; and
forming one or more deep trench isolation regions that extend through the one or more shallow trench isolation regions and the counter-doped second region of the epitaxial layer, wherein the one or more shallow trench isolation regions, the one or more deep trench isolation regions and the counter-doped second region of the epitaxial layer form an isolation region.
2. The method of claim 1 , further comprising:
fabricating a heterojunction bipolar transistor in a first portion of the first region of the epitaxial layer; and
fabricating a CMOS device in a second portion of the first region of the epitaxial layer, wherein the isolation region isolates the heterojunction bipolar transistor and the CMOS device.
3. The method of claim 1 , further comprising forming the one or more deep trench isolation regions in a grid, wherein the counter-doped second region of the epitaxial layer is located within the grid.
4. A method comprising:
growing an epitaxial layer over a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type and the epitaxial layer has a second conductivity type, opposite the first conductivity type;
forming a mask over the epitaxial layer, wherein the mask covers a first region of the epitaxial layer and exposes a second region of the epitaxial layer;
implanting a dopant having the first conductivity type through the mask into the second region of the epitaxial layer, whereby the second region of the epitaxial layer becomes counter-doped to the first conductivity type, wherein the implanting is performed such that the counter-doped second region of the epitaxial layer has a sheet resistance of at least about 50 KΩ/square; and
forming one or more shallow trench isolation regions in the counter-doped second region of the epitaxial layer, wherein portions of the counter-doped second region of the epitaxial layer are exposed through the one or more shallow trench isolation regions, and wherein the one or more shallow trench isolation regions and the counter-doped second region of the epitaxial layer form an isolation region.
5. A method comprising:
growing an epitaxial layer over a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type and the epitaxial layer has a second conductivity type, opposite the first conductivity type;
forming a mask over the epitaxial layer, wherein the mask covers a first region of the epitaxial layer and exposes a second region of the epitaxial layer;
implanting a dopant having the first conductivity type through the mask into the second region of the epitaxial layer, whereby the second region of the epitaxial layer becomes counter-doped to the first conductivity type;
forming one or more shallow trench isolation regions in the counter-doped second region of the epitaxial layer, wherein portions of the counter-doped second region of the epitaxial layer are exposed through the one or more shallow trench isolation regions, and wherein the one or more shallow trench isolation regions and the counter-doped second region of the epitaxial layer form an isolation region; and
fabricating a radio frequency (RF) switch in the semiconductor substrate, wherein the RF switch comprises a plurality of CMOS transistors.
6. A method comprising:
growing an epitaxial layer over a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type and the epitaxial layer has a second conductivity type, opposite the first conductivity type;
forming a mask over the epitaxial layer, wherein the mask covers a first region of the epitaxial layer and exposes a second region of the epitaxial layer;
implanting a dopant having the first conductivity type through the mask into the second region of the epitaxial layer, whereby the second region of the epitaxial layer becomes counter-doped to the first conductivity type;
forming one or more shallow trench isolation regions in the counter-doped second region of the epitaxial layer, wherein portions of the counter-doped second region of the epitaxial layer are exposed through the one or more shallow trench isolation regions, wherein forming the one or more shallow trench isolation regions comprises performing a chemical mechanical polishing (CMP) process that exposes the portions of the counter-doped second region of the epitaxial layer through the one or more shallow trench isolation regions, and wherein the one or more shallow trench isolation regions and the counter-doped second region of the epitaxial layer form an isolation region.
7. A method comprising:
growing an epitaxial layer over a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type and the epitaxial layer has a second conductivity type, opposite the first conductivity type;
forming a mask over the epitaxial layer, wherein the mask includes openings that define locations of shallow trench isolation regions to be formed;
etching into the epitaxial layer through the openings in the mask, thereby creating a plurality of shallow trenches, wherein thinned portions of the epitaxial layer remain below the shallow trenches;
implanting a dopant having the first conductivity type through the mask into the thinned portions of the epitaxial layer, whereby the thinned portions of the epitaxial layer are counter-doped to the first conductivity type; and
filling the shallow trenches with a dielectric material, thereby forming shallow trench isolation regions.
8. The method of claim 7 , further comprising forming one or more deep trench isolation regions through the epitaxial layer.
9. The method of claim 8 , further comprising forming the one or more deep trench isolation regions in a grid, wherein the counter-doped thinned portions of the epitaxial layer are located within the grid.
10. The method of claim 7 , further comprising fabricating a heterojunction bipolar transistor in the semiconductor substrate, wherein a first region of the epitaxial layer forms a collector region of the heterojunction bipolar transistor.
11. The method of claim 10 , wherein the heterojunction bipolar transistor is included in a power amplifier.
12. The method of claim 7 , wherein the implanting is performed such that the counter-doped thinned portions of the epitaxial layer have a sheet resistance of at least about 50 KΩ/square.
13. The method of claim 7 , further comprising fabricating a radio frequency (RF) switch in the semiconductor substrate, wherein the RF switch comprises a plurality of series-connected CMOS transistors.