Semiconductor devices
A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.
1. A semiconductor device, comprising:
a peripheral circuit on a substrate;
base layer patterns over the peripheral circuit, the base layer patterns spaced apart from each other by a separation layer pattern in a horizontal direction with respect to an upper surface of the substrate;
cell blocks on the base layer patterns, each of the cell blocks including:
channels extending in a vertical direction with respect to the upper surface of the substrate; and
gate lines spaced apart from each other in the vertical direction, each of the gate lines surrounding outer sidewalls of the channels;
a first connecting contact extending in the vertical direction, the first connecting contact in contact with an upper surface of each of the base layer patterns; and
a second connecting contact extending in the vertical direction between adjacent ones of the base layer patterns to be electrically connected to the peripheral circuit,
wherein an upper surface of one of the base layer patterns and an uppermost surface of the separation layer pattern are substantially coplanar with each other.
2. The semiconductor device of claim 1 , further comprising:
a connecting wire in contact with top surfaces of the first connecting contact and the second connecting contact.
3. The semiconductor device of claim 1 , further comprising:
a first impurity region at an upper portion of each of the base layer patterns,
wherein the first connecting contact is in contact with the first impurity region of each of the base layer patterns.
4. The semiconductor device of claim 1 , wherein top surfaces of the first connecting contact and the second connecting contact are substantially coplanar with each other, and a bottom surface of the second connecting contact is lower than a bottom surface of the first connecting contact.
5. The semiconductor device of claim 1 , wherein the separation layer pattern is disposed between adjacent ones of the base layer patterns.
6. The semiconductor device of claim 5 , wherein the separation layer pattern includes a first separation layer pattern and a second separation layer pattern crossing each other.
7. The semiconductor device of claim 5 , wherein the separation layer pattern extends in a first direction, and the first connecting contact is in contact with an upper surface of each of an edge portion of the base layer patterns adjacent to the separation layer pattern in a second direction perpendicular to the first direction.
8. The semiconductor device of claim 1 , further comprising:
a lower insulation layer on the substrate beneath the base layer patterns, the lower insulation layer covering the peripheral circuit.
9. The semiconductor device of claim 1 , further comprising:
a gate line cut pattern intersecting the gate lines in the vertical direction; and
a second impurity region at upper portions of the base layer patterns under the gate line cut pattern.
10. The semiconductor device of claim 9 , wherein each of the gate line cut pattern and the second impurity region extends in a direction crossing the separation layer pattern.
11. The semiconductor device of claim 10 , wherein the second impurity region is cut or separated by the separation layer pattern.
12. The semiconductor device of claim 9 , wherein each of the gate line cut pattern and the second impurity region extends in the same direction as an extension direction of the separation layer pattern.
13. The semiconductor device of claim 9 , wherein the gate line cut pattern overlaps the separation layer pattern along the vertical direction.
14. The semiconductor device of claim 9 , wherein the cell blocks are separated from each other by the gate line cut pattern.
15. The semiconductor device of claim 1 , further comprising:
a bit line electrically connected to the channels,
wherein the separation layer pattern extends in the same direction as an extension direction of the bit line.
16. A semiconductor device, comprising:
a peripheral circuit on a substrate;
base layer patterns over the peripheral circuit, the base layer patterns spaced apart from each other by a separation layer pattern in a first horizontal direction with respect to an upper surface of the substrate;
cell blocks on the base layer patterns spaced apart from each other by a gate line cut pattern in a second horizontal direction with respect to the upper surface of the substrate, each of the cell blocks including:
channels extending in a vertical direction with respect to the upper surface of the substrate; and
gate lines spaced apart from each other in the vertical direction, each of the gate lines surrounding outer sidewalls of the channels,
wherein each of the cell blocks includes sub-cell blocks separated from each other by the separation layer pattern;
a first connecting contact extending in the vertical direction on each of the base layer patterns in each sub-cell block; and
a second connecting contact extending through the separation layer pattern in the vertical direction to be electrically connected to the peripheral circuit, the second connecting contact electrically connected to the first connecting contact in each sub-cell block by a corresponding connecting wire.
17. The semiconductor device of claim 16 , further comprising:
a first impurity region at an upper portion of each of the base layer patterns in each sub-cell block,
wherein the first connecting contact is in contact with the first impurity region of each of the base layer patterns in each sub-cell block.
18. The semiconductor device of claim 16 , wherein the gate line cut pattern intersects the gate lines in the vertical direction, and
wherein the semiconductor device further comprises a second impurity region at upper portions of the base layer patterns under the gate line cut pattern.
19. A semiconductor device, comprising:
a peripheral circuit on a substrate;
base layer patterns over the peripheral circuit, the base layer patterns spaced apart from each other by a separation layer pattern in a horizontal direction with respect to an upper surface of the substrate;
channels extending in a vertical direction with respect to the upper surface of the substrate;
gate lines spaced apart from each other in the vertical direction, each of the gate lines surrounding outer sidewalls of the channels;
a first connecting contact extending in the vertical direction on each of the base layer patterns;
a second connecting contact extending through the separation layer pattern in the vertical direction to be electrically connected to the peripheral circuit, the second connecting contact electrically connected to the first connecting contact on each of the base layer patterns by a connecting wire; and
a common source line (CSL) contact extending in the vertical direction on each of the base layer patterns.
20. The semiconductor device of claim 19 , further comprising:
a CSL electrically connected to the CSL contact disposed in a first horizontal direction or a second horizontal direction with respect to the upper surface of the substrate,
wherein the separation layer pattern includes first and second portions extending in the first and second horizontal directions, respectively, and crossing each other.