IP Library Granted Patent US 10,217,752
Granted Patent B2
US 10,217,752 · App. 15/591,150 · Granted Feb 26, 2019

Semiconductor device

Inventors: Tomoaki Atsumi (Kanagawa, JP); Shuhei Nagatsuka (Kanagawa, JP); Tamae Moriwaka (Kanagawa, JP); Yuta Endo (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/115G11C7/16G11C8/14G11C11/24G11C11/403G11C11/4085H01L27/0688H01L27/1156H01L27/11551H01L29/24H01L29/7869
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Quick Facts
Patent No.
US 10,217,752
App. No.
15/591,150
Granted
Feb 26, 2019
Kind
B2
Abstract

[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

Claims (31)

1. A semiconductor device comprising:

a memory cell comprising a first transistor, a second transistor, and a capacitor,

wherein:

a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and one electrode of the capacitor,

the first transistor and the second transistor each comprise an oxide semiconductor layer containing indium (In), an element M, and zinc (Zn),

in the first transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by g:h:i (each of g, h, i is a positive number),

in the second transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by d:e:f (each of d, e, f is a positive number), and

g/(g+h+i) is smaller than d/(d+e+f).

2. The semiconductor device according to claim 1 , wherein the element M is aluminum, gallium, yttrium, or tin.

3. The semiconductor device according to claim 1 , wherein the first transistor is over the second transistor.

4. The semiconductor device according to claim 1 , wherein in a height direction, the capacitor is between the first transistor and the second transistor.

5. The semiconductor device according to claim 1 , wherein:

the second transistor has a higher mobility than the first transistor, and

the first transistor has a lower off-state current than the second transistor.

6. A semiconductor device comprising:

a first memory cell comprising a first transistor, a second transistor, and a capacitor; and

a second memory cell comprising a first transistor, a second transistor, and a capacitor,

wherein in each of the first and second memory cells:

a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and one electrode of the capacitor,

the first and second transistors each comprise an oxide semiconductor layer containing indium (In), an element M, and zinc (Zn),

in the first transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by g:h:i (each of g, h, i is a positive number),

in the second transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by d:e:f (each of d, e, f is a positive number), and

g/(g+h+i) is smaller than d/(d+e+f).

7. The semiconductor device according to claim 6 , wherein the second memory cell is over the first memory cell.

8. The semiconductor device according to claim 6 , wherein the element M is aluminum, gallium, yttrium, or tin.

9. The semiconductor device according to claim 6 ,

wherein the first transistor is over the second transistor in each of the first and second memory cells.

10. The semiconductor device according to claim 6 , wherein in a height direction the capacitor is between the first transistor and the second transistor in each of the first and second memory cells.

11. The semiconductor device according to claim 6 , wherein in each of the first and second memory cells:

the second transistor has a higher mobility than the first transistor, and

the first transistor has a lower off-slate current than the second transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2017
From: ATSUMI, TOMOAKI; NAGATSUKA, SHUHEI; MORIWAKA, TAMAE; ENDO, YUTA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 042790/0495 →
Priority Claims (1)
JP 2014-045406 · Mar 7, 2014 · national
Continuity (2)
Continuation 14637542 · Mar 4, 2015
Related Publication 20170243874A1 · Aug 24, 2017
Cited By (5)
US 12,260,898 US 12,300,752 US 12,426,378 US 12,453,073 US 12,531,114