IP Library Granted Patent US 12,453,073
Granted Patent B2
US 12,453,073 · App. 17/616,441 · Granted Oct 21, 2025

Semiconductor device

Inventors: Hitoshi Kunitake (Kanagawa, JP); Takayuki Ikeda (Kanagawa, JP); Takahiro Fukutome (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10B12/00H10D30/6734H10D30/6755H10D86/423H10D86/441H10D86/481H10D86/60H10D87/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,453,073
App. No.
17/616,441
Granted
Oct 21, 2025
Kind
B2
Abstract

A small-size semiconductor device is provided. The semiconductor device includes a first layer, a second layer, and a third layer formed over a substrate. A first transistor included in the first layer includes a first semiconductor layer containing Si. A second transistor included in the second layer includes a second semiconductor layer containing Ga. A third transistor included in the third layer includes a third semiconductor layer containing at least one of In and Zn. The first semiconductor layer of the first transistor is formed using the substrate. The second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate. The third semiconductor layer of the third transistor is formed above the first semiconductor layer and the second semiconductor layer.

Claims (53)

1. A semiconductor device comprising:

a first layer, a second layer, and a third layer over a substrate,

wherein a first transistor included in the first layer comprises a first semiconductor layer comprising Si,

wherein a second transistor included in the second layer comprises a second semiconductor layer comprising Ga,

wherein a third transistor included in the third layer comprises a third semiconductor layer comprising at least one of In and Zn,

wherein the first semiconductor layer of the first transistor is formed using the substrate,

wherein the second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate, and

wherein the third semiconductor layer of the third transistor is over the first semiconductor layer and the second semiconductor layer.

2. The semiconductor device according to claim 1 ,

wherein the third transistor comprises a region overlapping with the first transistor.

3. The semiconductor device according to claim 1 ,

wherein the third transistor comprises a region overlapping with the second transistor.

4. The semiconductor device according to claim 1 , further comprising a fourth layer,

wherein a fourth transistor included in the fourth layer comprises at least one of In and Zn in a fourth semiconductor layer, and

wherein the fourth transistor comprises a region overlapping with the third transistor.

5. The semiconductor device according to claim 1 ,

wherein a sensor module is placed on a side opposite to a side where the first transistor in the first layer is formed.

6. A semiconductor device comprising:

a first layer, a second layer, and a third layer over a substrate,

wherein a first transistor included in the first layer comprises a first semiconductor layer comprising Si,

wherein a second transistor included in the second layer comprises a second semiconductor layer comprising Ga,

wherein a third transistor included in the third layer comprises a third semiconductor layer comprising at least one of In and Zn,

wherein the first semiconductor layer of the first transistor is formed using the substrate,

wherein the second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate,

wherein the second transistor has a recessed gate structure, and

wherein the third semiconductor layer of the third transistor is over the first semiconductor layer and the second semiconductor layer.

7. The semiconductor device according to claim 6 ,

wherein the third transistor comprises a region overlapping with the first transistor.

8. The semiconductor device according to claim 6 ,

wherein the third transistor comprises a region overlapping with the second transistor.

9. The semiconductor device according to claim 6 , further comprising a fourth layer,

wherein a fourth transistor included in the fourth layer comprises at least one of In and Zn in a fourth semiconductor layer, and

wherein the fourth transistor comprises a region overlapping with the third transistor.

10. The semiconductor device according to claim 6 ,

wherein a sensor module is placed on a side opposite to a side where the first transistor in the first layer is formed.

11. A semiconductor device comprising:

a first layer, a second layer, and a third layer over a substrate,

wherein a first transistor included in the first layer comprises a first semiconductor layer comprising Si,

wherein a second transistor included in the second layer comprises a second semiconductor layer comprising oxygen,

wherein a third transistor included in the third layer comprises a third semiconductor layer comprising at least one of In and Zn,

wherein the first semiconductor layer of the first transistor is formed using the substrate,

wherein the second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate,

wherein the second transistor does not overlap with the first transistor, and

wherein the third semiconductor layer of the third transistor is over the first semiconductor layer and the second semiconductor layer.

12. The semiconductor device according to claim 11 ,

wherein the third transistor comprises a region overlapping with the first transistor.

13. The semiconductor device according to claim 11 ,

wherein the third transistor comprises a region overlapping with the second transistor.

14. The semiconductor device according to claim 11 , further comprising a fourth layer,

wherein a fourth transistor included in the fourth layer comprises at least one of In and Zn in a fourth semiconductor layer, and

wherein the fourth transistor comprises a region overlapping with the third transistor.

15. The semiconductor device according to claim 11 ,

wherein a sensor module is placed on a side opposite to a side where the first transistor in the first layer is formed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2021
From: KUNITAKE, HITOSHI; IKEDA, TAKAYUKI; FUKUTOME, TAKAHIRO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 058284/0187 →
Priority Claims (1)
JP 2019-107085 · Jun 7, 2019 · national
Continuity (1)
Related Publication 20220238525A1 · Jul 28, 2022
References Cited (55)
US 4774205A · Choi et al. · 1988 [cited by applicant]
US 8378391B2 · Koyama et al. · 2013 [cited by applicant]
US 8415731B2 · Yamazaki et al. · 2013 [cited by applicant]
US 8441047B2 · Godo et al. · 2013 [cited by applicant]
US 8809853B2 · Saito et al. · 2014 [cited by applicant]
US 8916869B2 · Koyama et al. · 2014 [cited by applicant]
US 9070758B2 · Van Hove · 2015 [cited by applicant]
US 9252258B2 · Van Hove · 2016 [cited by applicant]
US 9331112B2 · Koyama et al. · 2016 [cited by applicant]
US 9653611B2 · Atsumi et al. · 2017 [cited by applicant]
US 9660085B2 · Then et al. · 2017 [cited by applicant]
US 9773814B2 · Koyama et al. · 2017 [cited by applicant]
US 9818473B2 · Tsutsui · 2017 [cited by applicant]
US 10032911B2 · Then et al. · 2018 [cited by applicant]
US 10050015B2 · Pillarisetty · 2018 [cited by examiner]
US 10217752B2 · Atsumi et al. · 2019 [cited by applicant]
US 10580895B2 · Then et al. · 2020 [cited by applicant]
US 10593683B2 · Atsumi et al. · 2020 [cited by applicant]
US 11114449B2 · Atsumi et al. · 2021 [cited by applicant]
US 11751409B2 · Atsumi et al. · 2023 [cited by applicant]
US 20110089417A1 · Yamazaki et al. · 2011 [cited by applicant]
US 20110108836A1 · Koyama et al. · 2011 [cited by applicant]
US 20110227199A1 · Hata et al. · 2011 [cited by applicant]
US 20150325285A1 · Tsutsui · 2015 [cited by examiner]
US 20160308041A1 · Then et al. · 2016 [cited by applicant]
US 20210210964A1 · Cao · 2021 [cited by examiner]
US 20230371286A1 · Atsumi et al. · 2023 [cited by applicant]
CN 102598269A · 2012 [cited by applicant]
CN 105745759A · 2016 [cited by applicant]
EP 0250171A · 1987 [cited by applicant]
EP 2497111A · 2012 [cited by applicant]
EP 2541605A · 2013 [cited by applicant]
EP 3051588A · 2016 [cited by applicant]
EP 3087612A · 2016 [cited by applicant]
JP 63018661A · 1988 [cited by applicant]
JP 2010153845A · 2010 [cited by applicant]
JP 2013012735A · 2013 [cited by applicant]
JP 2015144284A · 2015 [cited by applicant]
JP 2015181159A · 2015 [cited by applicant]
JP 2015188071A · 2015 [cited by applicant]
JP 2016009774A · 2016 [cited by applicant]
JP 2017501562 · 2017 [cited by applicant]
JP 2017510979 · 2017 [cited by applicant]
JP 2018201003A · 2018 [cited by applicant]
JP 2019009462A · 2019 [cited by applicant]
KR 20120091294A · 2012 [cited by applicant]
KR 20160100925A · 2016 [cited by applicant]
WO WO2011055626 · 2011 [cited by applicant]
WO WO2015099688 · 2015 [cited by applicant]
WO WO2015147835 · 2015 [cited by applicant]
International Search Report (Application No. PCT/IB2020/054923) Dated Sep. 8, 2020. [cited by applicant]
Written Opinion (Application No. PCT/IB2020/054923) Dated Sep. 8, 2020. [cited by applicant]
Yamazaki.S et al., “Research, Development, and Application of Crystalline Oxide Semiconductor”, SID Digest '12 : SID International Symposium Digest of Technical Papers, Jun. 5, 2012, vol. 43, No. 1, pp. 183-186. [cited by applicant]
Yamazaki.S et al., “Properties of crystalline In—Ga—Zn-oxide semiconductor and its transistor characteristics”, Jpn. J. Appl. Phys. (Japanese Journal of Applied Physics) , Mar. 31, 2014, vol. 53, No. 4S, pp. 04ED18-1-04… [cited by applicant]
Inoue.K et al., “GaN HEMT Linearity Improvement for Wireless Communication Applications”, SEI Technical Review, 2014, No. 184, pp. 44-49, Sumitomo Electric. [cited by applicant]