Method of forming a P-type layer for a light emitting device

1. A method comprising:

growing a semiconductor structure comprising at least one III-nitride light emitting layer, at least one p-type region and at least one n-type region, the at least one p-type region being buried below the at least one n-type region within the semiconductor structure, selectively growing the semiconductor structure to form a trench that exposes a portion of the at least one p-type region; and

after forming the trench, annealing the semiconductor structure, wherein selectively growing the semiconductor structure comprises:

forming a plurality of sections of mask material on a surface of the at least one p-type region;

growing the semiconductor structure around the plurality of sections of mask material; and

after said growing the semiconductor structure around the plurality of sections of mask material, removing the plurality of sections of mask material.

2. The method of claim 1 , further comprising, after said annealing the semiconductor structure, filling the trench with an insulating material.

3. The method of claim 2 , further comprising filling the trench with an insulating material such that the insulating material is in contact with the at least one n-type region and the at least one p-type region.

4. The method of claim 1 , further comprising:

disposing a metal in the trench, wherein the metal is in direct contact with a first portion of the semiconductor structure in the trench, and an insulating layer is disposed between the metal and a second portion of the semiconductor structure in the trench.

5. The method of claim 1 , further comprising forming a plurality of trenches.

6. The method of claim 5 , wherein each trench is completely surrounded by at least a portion of the semiconductor structure that is uninterrupted by the trench.

7. The method of claim 5 , wherein nearest neighbor trenches are spaced less than twice a maximum length of diffusion of hydrogen during said annealing the semiconductor structure.

8. The method of claim 1 , wherein the semiconductor structure comprises a tunnel junction.

9. The method of claim 1 , wherein the at least one p-type region is buried below the at least one n-type region such that the entire at least one p-type region is buried below the at least one n-type region.

10. The method of claim 1 , wherein the trench extends through the semiconductor structure.

11. The method of claim 1 , wherein removing the plurality of sections of mask material comprises completely removing the plurality of sections of mask material.

12. A method of forming a device, the method comprising:

growing a p-type layer;

forming a mask layer in contact with at least one portion of the p-type layer, the mask layer enabling removal of hydrogen from the p-type layer;

growing a n-type layer on the mask layer and the p-type layer;

annealing the device; and

forming at least one embedded trench by removing the mask layer, the at least one embedded trench exposing the at least one portion of the p-type layer to an ambient environment.

13. The method of claim 12 , wherein the at least one embedded trench is a lateral embedded trench.

14. The method of claim 12 , wherein the at least one embedded trench is a vertical embedded trench.

15. The method of claim 12 , wherein the at least one embedded trench is a combination of lateral embedded trenches and vertical embedded trenches.

16. The method of claim 12 , wherein the mask layer is a plurality of mask regions, each mask region being in contact with a portion of the p-type layer.

17. The method of claim 12 , further comprising:

filling the at least one trench with an insulating material.

18. The method of claim 12 , wherein the at least one embedded trench is surrounded by portions of at least one of the p-type layer or n-type layer that are uninterrupted by the at least one embedded trench.

19. The method of claim 12 , wherein nearest neighbor trenches are spaced less than twice a maximum length of diffusion of hydrogen during an annealing process.

20. The method of claim 12 , further comprising:

growing tunnel junctions on the p-type layer.

21. A method comprising:

growing a semiconductor structure comprising at least one III-nitride light emitting layer, at least one p-type region and at least one n-type region, the at least one p-type region being buried below the at least one n-type region within the semiconductor structure, selectively growing the semiconductor structure to form a plurality of trenches that expose a portion of the at least one p-type region, such that at least one trench extends through the at least one n-type region and terminates at a bottom comprising the at least one p-type region; and

after forming the plurality of trenches, annealing the semiconductor structure, wherein each trench is completely surrounded by at least a portion of the semiconductor structure that is uninterrupted by the trench.

22. A method comprising:

growing a semiconductor structure comprising at least one III-nitride light emitting layer, at least one p-type region and at least one n-type region, the at least one p-type region being buried below the at least one n-type region within the semiconductor structure, selectively growing the semiconductor structure to form a plurality of trenches that expose a portion of the at least one p-type region, such that at least one trench extends through the at least one n-type region and terminates at a bottom comprising the at least one p-type region; and

after forming the plurality of trenches, annealing the semiconductor structure, wherein nearest neighbor trenches are spaced less than twice a maximum length of diffusion of hydrogen during said annealing the semiconductor structure.