Vertical power transistor with deep trenches and deep regions surrounding cell array
Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
1. A vertical transistor comprising:
a cell array formed in a first semiconductor material of a first conductivity type, the cell array comprising vertical gates and a body region of a second conductivity type between the vertical gates, wherein the body region is configured for being inverted proximate to a vertical gate, when the vertical gate is electrically biased, for creating a conductive channel for turning on the transistor;
at least one first trench formed in the first semiconductor material surrounding the cell array, wherein the at least one first trench is deeper than the vertical gates;
a deep region of the second conductivity type, the deep region abutting at least a bottom portion of the first trench and extending below the first trench, the deep region being deeper than the body region and having a dopant concentration that is lower than a dopant concentration of the body region;
a substrate of the second conductivity type vertically separated by the deep region at least by the first semiconductor material;
a first electrode formed on a bottom surface of the substrate; and
a second electrode formed overlying at least portions of the cell array.
2. The transistor of claim 1 wherein the deep region is floating.
3. The transistor of claim 1 wherein the at least one first trench comprises a plurality of concentric first trenches surrounding the cell array, where each of the first trenches has an associated deep region of the second conductivity type below it, the transistor further comprising:
first regions of the second conductivity type between the first trenches and connecting together adjacent ones of the deep regions, the first regions being shallower than the deep regions but deeper than the body region, wherein the deep regions and first regions form a shield area around the cell array, wherein the shield area has a breakdown voltage lower than a breakdown voltage of the cell array.
4. The transistor of claim 3 wherein the deep regions and the first regions are electrically coupled to the second electrode.
5. The transistor of claim 3 wherein the cell array comprises:
second trenches, shallower than the first trenches, wherein the second trenches are at least partially filled with a conductive gate material to form the vertical gates;
a source region of the first conductivity type between the second trenches, the source region being electrically coupled to the second electrode; and
the body region of the second conductivity type between the second trenches, the body region being located between the source region and the first semiconductor material and configured to be inverted by the vertical gates when the vertical gates are biased to form the conductive channel between the source region and the first semiconductor region to turn on the transistor.
6. The transistor of claim 5 wherein the concentric first trenches are wider than the second trenches in the cell array.
7. The transistor of claim 3 wherein the cell array is formed as a two-dimensional array of cells surrounded by the concentric first trenches.
8. The transistor of claim 3 wherein the cell array is formed as strips of cells, where each strip of cells is surrounded by the concentric first trenches.
9. The transistor of claim 3 further comprising a conductive material at least partially filling the first trenches, wherein the conductive material filling the first trenches is electrically connected to the vertical gates in the cell array.
10. The transistor of claim 3 wherein the deep regions form equipotential rings around the cell array.
11. The transistor of claim 3 further comprising a first contact region of the second conductivity type formed in the first regions, wherein the first contact region is electrically coupled to the second electrode.
12. The transistor of claim 3 further comprising a second region of the second conductivity type between an innermost one of the first trenches and the cell array, the second region being electrically coupled to the second electrode, the second region being shallower than the first regions.
13. The transistor of claim 3 where in the transistor is formed as a die, the transistor further comprising a termination area surrounding the concentric first trenches, wherein the termination area is located between the concentric first trenches and an edge of the transistor die for reducing electric field crowding proximate to an edge of the die.
14. The transistor of claim 3 further comprising a conductive material at least partially filling the first trenches.
15. The transistor of claim 3 wherein dopants of the second conductivity type are implanted through the concentric first trenches to form the deep regions, causing the deep regions to be aligned with the first trenches.
16. The transistor of claim 1 wherein the at least one first trench is filled with a dielectric material.
17. The transistor of claim 1 wherein the at least one first trench comprises a plurality of concentric first trenches surrounding the cell array, where each of the first trenches has an associated deep region of the second conductivity type below it, wherein the concentric first trenches are filled with a dielectric material, the transistor further comprising:
floating metal rings above the first trenches acting as floating field plates, wherein the dielectric material within the first trenches acts as a vertical spacer between the metal rings and the deep regions for controlling a shape of a depletion region surrounding the cell array.
18. The transistor of claim 1 wherein the transistor is an insulated gate bipolar transistor.
19. The transistor of claim 1 wherein the substrate comprises a growth substrate for the first semiconductor material.