IP Library › Granted Patent US 10,355,071
Granted Patent B2
US 10,355,071 · App. 15/593,479 · Granted Jul 16, 2019

Semiconductor device and a method for fabricating the same

Inventors: Yu-Chiun Lin (Taipei, TW); Po-Nien Chen (Miaoli, TW); Chen Hua Tsai (Hsinchu County, TW); Chih-Yung Lin (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L28/24H01L21/32051H01L23/5228H01L27/0207H01L27/0629H01L29/1079H01L29/1095H01L21/823431H01L21/823493H01L29/66545H01L29/7851
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Quick Facts
Patent No.
US 10,355,071
App. No.
15/593,479
Granted
Jul 16, 2019
Kind
B2
Abstract

A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Claims (53)

1. A semiconductor device, comprising:

a substrate having a first conductivity type;

an isolation insulating layer formed in the substrate;

a first well formed in the substrate and having a second conductivity type, a part of the first well extending below the isolation insulating layer;

a first diffusion region formed in the first well and having the first conductivity type;

a first interlayer dielectric layer disposed over the first well and the first diffusion region;

a dummy structure disposed over the first well; and

a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer,

wherein the resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view, and

the first well is electrically floating, and

the resistor wire overlaps the dummy structure in plan view.

2. The semiconductor device of claim 1 , wherein the conductive material of the resistor wire includes a transition metal nitride.

3. The semiconductor device of claim 1 , wherein the conductive material of the resistor wire includes at least one of TiN, TaN, W and Co.

4. The semiconductor device of claim 1 , wherein:

the dummy structure includes two or more dummy gate electrodes disposed over the first well and extending in a first direction and arranged in a second direction perpendicular to the first direction, and

the resistor wire extends in the first direction.

5. The semiconductor device of claim 4 , wherein the resistor wire is longer than the dummy gate electrodes along the first direction.

6. The semiconductor device of claim 4 , wherein:

the dummy structure includes two dummy gate electrodes, and

the first diffusion region is disposed between the two dummy gate electrodes.

7. The semiconductor device of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

8. The semiconductor device of claim 1 , further comprising a second well of the second conductivity type formed in the substrate,

wherein the first well is formed in the second well.

9. A semiconductor device, comprising:

a substrate having a first conductivity type;

an intermediate layer formed over the substrate and made of non-doped or intrinsic semiconductor;

a first diffusion region of the first conductivity type formed in the intermediate layer;

a first interlayer dielectric layer disposed over the intermediate layer and the first diffusion region;

a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer,

wherein the resistor wire overlaps the first diffusion region and at least partially overlaps the intermediate layer in plan view.

10. The semiconductor device of claim 9 , further comprising a dummy structure disposed over the intermediate layer,

wherein the resistor wire overlaps the dummy structure in plan view.

11. The semiconductor device of claim 9 , wherein the conductive material of the resistor wire includes a nitride of a transition metal.

12. The semiconductor device of claim 9 , wherein the conductive material of the resistor wire includes at least one of TiN, TaN, W and Co.

13. The semiconductor device of claim 9 , wherein:

the dummy structure includes two or more dummy gate electrodes disposed over the intermediate layer and extending in a first direction and arranged in a second direction perpendicular to the first direction, and

the resistor wire extends in the first direction.

14. The semiconductor device of claim 13 , wherein the resistor wire is longer than the dummy gate electrodes along the first direction.

15. The semiconductor device of claim 13 , wherein:

the dummy structure includes two dummy gate electrodes, and

the first diffusion region is disposed between the two dummy gate electrodes.

16. The semiconductor device of claim 9 , wherein the first conductivity type is p-type.

17. A method of manufacturing a semiconductor device, the method comprising:

forming a first well in a substrate, the substrate having a first conductivity type and the first well having a second conductivity type;

forming a first diffusion region having the first conductivity type;

forming dummy gate electrodes made of a conductive material over the first well;

forming a first interlayer dielectric (ILD) layer over the first well, the first diffusion region and the dummy gate electrodes;

forming a resistor wire over the first ILD layer;

forming a second interlayer dielectric layer over the first interlayer dielectric layer and the resistor wire, wherein:

the resistor wire is made of a conductive material, and

the resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

18. The method of claim 17 , wherein the conductive material of the resistor wire includes at least one of TiN, TaN, W and Co.

19. The method of claim 17 , wherein each of the dummy gate electrodes includes a metal gate electrode and a cap insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2017
From: LIN, YU-CHIUN; CHEN, PO-NIEN; TSAI, CHEN HUA; LIN, CHIH-YUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 042350/0569 →
Continuity (2)
Provisional Application 62440081 · Dec 29, 2016
Related Publication 20180190754A1 · Jul 5, 2018