Circuit to perform dual input value absolute value and sum operation

1. An execution unit circuit, comprising a pair of arithmetic logic units (ALUs) configured to perform a sum of absolute difference computation, wherein the pair of ALUs comprise:

a first ALU that comprises a first input to receive a first input value X and a second input to receive a second input value Y, and

a second ALU that comprises a third input to receive a third input value Z and a fourth input to receive an output of the first ALU,

wherein the execution unit circuit is configured to perform a sum of absolute difference computation using ALU operations comprising:

computing, by the first ALU of the pair of ALUs, a difference value Q between the first input value X and the second input value Y,

computing a result of the sum of absolute difference computation including:

adding, by the second ALU of the pair of ALUs, a sum of the third input value Z to the difference value Q whenever Q is positive, or

subtracting, by the second ALU of the pair of ALUs, the difference value Q from the third input value Z whenever Q is negative, and

outputting the computed result of the sum of absolute difference computation.

2. The execution unit circuit of claim 1 , wherein the circuitry second ALU comprises an adder circuit.

3. The execution unit circuit of claim 1 , wherein the execution unit circuit is configured to compute the sum of absolute difference computation in response to receiving a single instruction.

4. The execution unit circuit of claim 3 , wherein the execution unit circuit is configured to compute the sum of absolute difference computation using at most two ALU operations.

5. The execution unit circuit of claim 1 , wherein the execution unit circuit is configured to execute an absolute difference instruction that when executed causes the execution unit circuit to compute an absolute difference between a first value specified by a first input operand of the absolute difference instruction and a second value specified by a second input operand of the absolute difference instruction,

wherein during execution of the absolute difference instruction, the second ALU is configured to receive a difference between the first value and the second value computed by the first ALU and to perform operations comprising:

adding a zero value to the difference whenever the difference is positive, or

subtracting the difference from a zero value whenever the difference is negative.

6. The execution unit circuit of claim 5 , wherein the second ALU is configured to receive the zero value from external register space of the execution unit circuit.

7. The execution unit circuit of claim 3 , wherein the third input value Z is specified as an operand of the single instruction.

8. A method for performing a sum of absolute difference computation by an execution unit circuit comprising a pair of arithmetic logic units (ALUs), wherein the method comprises:

receiving, by a first ALU of the pair of ALUs, a first input value X and a second input value Y;

computing, by the first ALU of the pair of ALUs, a difference value Q between the first input value X and the second input value Y;

receiving, by a second ALU of the pair of ALUs, a third input value Z and the difference value Q output by the first ALU;

computing a result of the sum of absolute difference computation including:

adding, by the second ALU of the pair of ALUs, a sum of the third input value Z to the difference value Q whenever Q is positive, or

subtracting, by the second ALU of the pair of ALUs, the difference value Q from the third input value Z whenever Q is negative; and

outputting the computed result of the sum of absolute difference computation.

9. The method of claim 8 , wherein the second ALU comprises an adder circuit.

10. The method of claim 8 , wherein the execution unit circuit performs the sum of absolute difference computation in response to receiving a single instruction.

11. The method of claim 10 , wherein the execution unit circuit performs the sum of absolute difference computation using at most two ALU operations.

12. The method of claim 10 , wherein the third input value Z is specified as an operand of the single instruction.

13. The method of claim 8 , further comprising:

executing, by the execution unit, an absolute difference instruction between a first value specified by a first input operand of the absolute difference instruction and a second value specified by a second input operand of the absolute difference instruction, including:

receiving, by the second ALU, a difference between the first value and the second value computed by the first ALU; and

adding a zero value to the difference whenever the difference is positive, or

subtracting the difference from a zero value whenever the difference is negative.

14. The method of claim 13 , further comprising receiving, by the second ALU, the zero value from external register space of the execution unit circuit.

15. An image processor comprising a plurality of execution unit circuits, wherein each execution unit circuit comprises:

a first input to receive a first input value X;

a second input to receive a second input value Y;

a third input to receive a third input value Z; and

means for computing a sum of absolute difference computation from the first input value X, the second input value Y, and the third input value Z using at most two arithmetic logic unit operations.

16. The image processor of claim 15 , wherein each execution unit circuit comprises respective means for computing the sum of absolute difference computation in response to receiving a single instruction.