IP Library Granted Patent US 10,388,688
Granted Patent B2
US 10,388,688 · App. 15/595,356 · Granted Aug 20, 2019

Method of forming a shallow pinned photodiode

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Quick Facts
Patent No.
US 10,388,688
App. No.
15/595,356
Granted
Aug 20, 2019
Kind
B2
Abstract

An image sensor with a pinned photodiode includes a photodiode formed in a substrate by implanting dopants of a first type through one or more dielectric layers formed over the substrate. A pinning layer for the photodiode may be formed by implanting dopants of a second type through the same one or more dielectric layers. The pinning layer may be formed over a photodiode region of the substrate. The concentration of dopants of the second type may have a maximum value in dielectric layers over the photodiode that exceeds the concentration of dopants of the second type in the substrate below. The photodiode and pinning layer may both be formed by implanting ions of the first and second type respectively through a dielectric layer formed after etching away a portion of another dielectric layer, having a different thickness, and having different optical transmission properties than the another dielectric layer.

Claims (32)

1. A method comprising:

forming a dielectric layer over an upper surface of a substrate;

implanting dopants of a first type into a channel implant region of the substrate through the dielectric layer;

forming a conductive structure over only a portion of the dielectric layer;

etching away exposed portions of the dielectric layer, wherein the exposed portions of the dielectric layer are formed above photodiode regions of the substrate;

after etching away the exposed portions of the dielectric layer, forming additional dielectric layers over the photodiode regions of the substrate; and

after etching away the exposed portions of the dielectric layer, implanting dopants of the first type into the photodiode regions of the substrate.

2. The method defined in claim 1 , wherein the exposed portions of the dielectric layer are not covered by the conductive structure.

3. The method defined in claim 1 , wherein implanting dopants of the first type into the photodiode regions of the substrate comprises implanting dopants of the first type into the photodiode regions of the substrate through the additional dielectric layers.

4. The method defined in claim 3 , wherein implanting dopants of the first type into the photodiode regions comprises:

implanting a maximum concentration of the first type of dopants within the photodiode region of the substrate.

5. The method defined in claim 1 , further comprising:

implanting dopants of a second type into a pinning region of the substrate, wherein the pinning region is formed above the photodiode region of the substrate.

6. The method defined in claim 5 , wherein implanting dopants of the second type comprises:

implanting a maximum concentration of the second type of dopants within the additional dielectric layers.

7. A method comprising:

forming a dielectric layer over an upper surface of a substrate;

implanting dopants of a first type into a channel implant region of the substrate through the dielectric layer;

forming a conductive structure over only a portion of the dielectric layer;

etching away exposed portions of the dielectric layer, wherein the exposed portions of the dielectric layer are formed above photodiode regions of the substrate;

implanting dopants of the first type directly into the photodiode regions of the substrate after etching away the exposed portions of the dielectric layer; and

forming additional dielectric layers over the photodiode regions of the substrate.

8. A method comprising:

forming a dielectric layer over an upper surface of a substrate;

forming a conductive structure over the dielectric layer, wherein the conductive structure has an opening;

implanting dopants of a first type through the opening in the conductive structure into the substrate to form a photodiode;

etching away portions of the dielectric layer that are exposed through the opening in the conductive structure;

forming at least one additional dielectric layer over the substrate; and

implanting dopants of a second type into a pinning region, wherein the pinning region has a concentration of the dopants of the second type greater than 1E18 atoms per cubic centimeter in the at least one additional dielectric layer and a concentration of the dopants of the second type less than 1E18 atoms per cubic centimeter in the substrate.

9. The method defined in claim 8 , wherein the doping profile of the pinning region has a maximum concentration of the dopants of the second type implanted within the at least one additional dielectric layer.

10. The method defined in claim 8 , further comprising:

before forming the conductive structure over the dielectric layer, implanting dopants of the first type into a channel implant region of the substrate through the dielectric layer.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 044481, FRAME 0594 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064074/0363 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0594 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2017
From: STEVENS, ERIC G.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042381/0748 →