Self-management memory system and operating method thereof
A semiconductor memory system and an operating method thereof include a controller configured to perform macro management; and a memory device including Nand pages, counters, a self-management component, and devoted memories, wherein the memory device is coupled and controlled by the controller, the Nand pages contains data corresponding to commands received from the controller, the counters are configured to track operation information corresponding to the Nand pages in accordance with the commands, the devoted memories are configured to record recovery information, and the self-management component configured to perform micro management in accordance at least in part with the operation information or the recovery information.
1. A semiconductor memory system comprising:
a memory controller configured to perform macro management; and
a flash memory component including Nand pages, counters, a self-management component, and devoted memories, wherein
the flash memory component is coupled with and controlled by the memory controller,
the Nand pages comprises data corresponding to commands received from the memory controller,
the counters are configured to track operation information corresponding to the Nand pages,
the devoted memories are configured to record recovery information, and
the self-management component is external to the memory controller and configured to perform, without further instruction from the memory controller, a subset of all operations performed on the Nand pages based on the operation information, the subset including micro management level operations including tracking a number of program/erase cycles and tracking extensive reads on pages of memory blocks in the flash memory component to reduce read disturb.
2. The system recited in claim 1 wherein the self-management component includes a simple CPU-like processor.
3. The system recited in claim 1 wherein the Nand pages comprises a plurality of pages and blocks.
4. The system recited in claim 1 wherein the counters comprise a plurality of counters, each of the plurality of counters is designated to at least a page or a block of the Nand pages.
5. The system recited in claim 1 wherein the operation information comprises numbers of read operation, numbers of write operation, numbers of erase operation, numbers of program/erase (PE) cycles, or a combination thereof.
6. The system recited in claim 1 wherein the devoted memories are configured with various sizes and locations.
7. The system recited in claim 1 wherein the recovery information comprises last written page addresses, previous read addresses, previous read data, extensive reads on a particular page, or a combination thereof.
8. The system recited in claim 1 wherein the micro management level operations performed by the self-management component further comprise bookkeeping, tracking addresses of last written pages, tracking damaged pages, or a combination thereof.
9. The system recited in claim 1 wherein the macro management performed by the memory controller comprises upper level tasks including garbage collection, wear-leverage, end of life handling, or a combination thereof.
10. The system recited in claim 1 wherein the operation information or the recovery information is provided to the memory controller.
11. An operating method of a semiconductor memory system comprising:
performing macro management by a memory controller;
tracking operation information corresponding to Nand pages in accordance with commands received from the memory controller by counters of a flash memory component;
recording recovery information by devoted memories of the flash memory component; and
performing, by a self-management component without further instruction from the memory controller, subset of all operations performed on the Nand pages based on the operation information, the subset including micro management level operations including tracking a number of program/erase cycles and tracking extensive reads on pages of memory blocks in the flash memory component to reduce read disturb;
wherein the a self-management component is external to the memory controller.
12. The method recited in claim 11 the self-management component includes a simple CPU-like processor.
13. The method recited in claim 11 wherein the tracking operation information includes tracking operation information of Nand pages comprising a plurality of pages and blocks.
14. The method recited in claim 11 wherein the tracking operation information comprises tracking operation information by a plurality of counters, each of the plurality of counters is designated to at least a page or a block in Nand pages.
15. The method recited in claim 11 wherein the tracking operation information comprises tracking numbers of read operation, numbers of write operation, numbers of erase operation, numbers of program/erase (PE) cycles, or a combination thereof.
16. The method recited in claim 11 wherein the recording recovery information by the devoted memories includes recording recovery information by the devoted memories with various sizes and locations.
17. The method recited in claim 11 wherein the recording recovery information includes the recording the recovery information of last written page addresses, previous read addresses, previous read data, extensive reads on a particular page, or a combination thereof.
18. The method recited in claim 11 wherein the micro management level operations further comprise bookkeeping, tracking addresses of last written pages, tracking damaged pages, or a combination thereof.
19. The method recited in claim 11 wherein the performing macro management by the memory controller comprises performing macro management of upper level tasks including garbage collection, wear-leverage, end of life handling, or a combination thereof.
20. The method recited in claim 11 further comprising providing the operation information or the recording recovery information to the memory controller.