IP Library Granted Patent US 10,170,028
Granted Patent B2
US 10,170,028 · App. 15/595,641 · Granted Jan 1, 2019

Data transmission system including encoder and a clock recovery system for display device, data transmission method for display device and display device

Inventors: Akio Sugiyama (Tokyo, JP); Takashi Nose (Tokyo, JP); Yoshihiko Hori (Tokyo, JP); Hirobumi Furihata (Tokyo, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
G09G3/2018G06F13/00G09G5/008G09G5/18H04L25/49H04L25/4908H04N7/01G09G3/2096G09G2310/027G09G2310/08G09G2320/064G09G2330/06G09G2360/127G09G2360/16G09G2370/00
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Quick Facts
Patent No.
US 10,170,028
App. No.
15/595,641
Granted
Jan 1, 2019
Kind
B2
Abstract

A data transmission system for a display device, the data transmission system comprising: an encoder having at least one translation table, encoding m bits of a data into n bits of a data on the basis of the translation table; a parallel-to-serial converter; a clock recovery circuit for recovering a clock from the data encoded and serialized; a serial-to-parallel converter for decoding the n bits of the encoded data to the m bits of the data; and an output driver for outputting a gray scale voltage, wherein an amplitude of the gray scale voltage is determined according to a value of the m bit of the data, and, wherein in the translation table, a larger the amplitude of the gray scale voltage of a bit pattern in 2 m pieces of bit patterns of the m bits of the data, a larger the data change index of the bit pattern.

Claims (19)

1. A data transmission system for a display device, the data transmission system comprising:

an encoder including at least one translation table, and encoding m (m is a natural number) bits of a data into n (n is a natural number and n>m) bits of a data on a basis of the translation table;

a parallel-to-serial converter for subjecting the encoded data outputted from the encoder to a parallel-to-serial conversion;

a clock recovery circuit for recovering a clock from the data encoded by the encoder and serialized by the parallel-to-serial converter;

a serial-to-parallel converter for subjecting the data outputted from the parallel-to-serial converter to a serial-to-parallel conversion;

a decoder for decoding the n bits of the encoded data to the m bits of the data in accordance with the clock recovered by the clock recovery circuit; and

an output driver for outputting a gray scale voltage in accordance with the data decoded by the decoder,

wherein an amplitude of the gray scale voltage is determined according to a value of the m bit of the data, and

wherein, in the translation table, a larger the amplitude of the gray scale voltage of a bit pattern in 2 m pieces of bit patterns of them bits of the data, a larger a data change index of the bit pattern which is assigned to the bit pattern in the 2 m pieces of bit patterns in 2 n pieces of bit patterns of the n bits of the data.

2. The data transmission system for a display device according to claim 1 , wherein, in the at least one translation table, the encoder includes a first translation table for a normally black mode as the translation table, a larger a data value of the bit pattern in 2 m pieces of the bit patterns of the m bits of the data, a larger the data change index of the bit pattern which is assigned to the bit pattern in the 2 m pieces of bit patterns in the 2 n pieces of the bit patterns of the n bits of the data.

3. The data transmission system for a display device according to claim 1 , wherein the encoder includes a second translation table for a normally white mode as the translation table, and in the second translation table, a smaller a data value of the bit pattern in the 2 m pieces of the bit patterns of the m bits of the data, a larger the data change index of the bit pattern which is assigned to the bit pattern in the 2 m pieces of bit patterns in the 2 n pieces of the bit patterns of the n bits of the data.

4. The data transmission system for a display device according to claim 1 , further comprising:

a data generating circuit for regularly converting or inversely converting the data inputted to the encoder in accordance with a first display mode signal; and

a data converter for regularly converting or inversely converting the data outputted from the decoder in accordance with a second display mode,

wherein the translation table is only one translation table for a normally black mode or for a normally white mode.

5. The data transmission system for a display device according to claim 4 , further comprising:

a first register for storing the first display mode signal; and

a second register for storing the second display mode signal.

6. The data transmission system for a display device according to claim 4 , wherein the first and the second display modes comprise signals indicating the normally black mode or the normally white mode.

Assignments (1)
CHANGE OF ADDRESS Recorded Dec 18, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 045764/0902 →
Priority Claims (1)
JP 2011-073122 · Mar 29, 2011 · national
Continuity (3)
Continuation 14726904 · Jun 1, 2015
Continuation 13431859 · Mar 27, 2012
Related Publication 20170250843A1 · Aug 31, 2017