Memory system having optimal threshold voltage and operating method thereof
A semiconductor memory system and an operating method thereof include a memory device; and a memory controller including a sequence generator, a sequence analyzer, and a processor coupled to the memory device and containing instructions executed by the processor, and configured to generate a sequence by the sequence generator, wherein the sequence comprises a sequence of digital data, write the sequence associated with a user data to the memory device, read out a read data including the sequence and the associated user data, analyze the sequence to understand characters of the read data and create analysis result by the sequence analyzer, identify an optimal threshold voltage in accordance with the analysis result, and provide the optimal threshold voltage to an ECC engine.
1. A semiconductor memory system comprising:
a memory device; and
a memory controller including a sequence generator, a sequence analyzer, and a processor, the memory controller being coupled to the memory device and containing instructions for execution by the processor to
generate a training sequence, using the sequence generator, for analysis of user data, wherein the training sequence comprises a sequence of digital data that is randomly generated, has a length indicative of a level of accuracy of analysis and is known to the memory system,
write the training sequence with the associated user data to the memory device,
read out the training sequence and the associated user data,
analyze the training sequence, using the sequence analyzer, to understand characters of the user data and create an analysis result,
identify an optimal threshold voltage in accordance with the analysis result, and
use the optimal threshold voltage in an error correction coding process.
2. The system of claim 1 wherein the training sequence is generated in accordance with configuration of the memory system.
3. The system of claim 1 wherein the randomly generated training sequence is evenly distributed with zeros and ones.
4. The system of claim 1 wherein the optimal threshold voltage includes multiple optimal threshold voltages when the memory system is a multi-level cell (MLC) memory system.
5. The system of claim 1 wherein the sequence generator includes a scrambler scrambling inputs thereof with a key or address.
6. The system of claim 1 wherein the sequence generator receives as inputs patterns from which the training sequence is generated.
7. The system of claim 1 wherein the training sequence is written in front of, in the middle of, or after the associated user data therewith.
8. The system of claim 1 wherein the sequence analyzer analyzing the training sequence includes comparing the sequence read out from the memory device with the training sequence generated by the sequence generator.
9. The system of claim 1 wherein the memory controller configured to identify the optimal threshold voltage includes identifying at least one threshold voltage to be adjusted and applying an appropriate voltage amount thereto.
10. The system of claim 9 wherein the memory controller configured to identify the optimal threshold voltage includes conducting at least one identifying and adjusting iterations until reaching desired results.
11. A method of operating a semiconductor memory system comprising:
generating a training sequence by a sequence generator, for analysis of user data, wherein the training sequence comprises a sequence of digital data that is randomly generated, has a length indicative of a level of accuracy of analysis and is known to the memory system;
writing the training sequence with the associated user data to a memory device;
reading out the training sequence and the associated user data;
analyzing the training sequence, using a sequence analyzer, to understand characters of the user data and creating an analysis result;
identifying an optimal threshold voltage in accordance with the analysis result; and
using the optimal threshold voltage in an error correction coding process.
12. The method of claim 11 wherein the training sequence is generated in accordance with an accuracy request of the memory system.
13. The method of claim 11 wherein the randomly generated training sequence is evenly distributed with zeros and ones.
14. The method of claim 11 wherein the identifying the optimal threshold voltage includes identifying multiple optimal threshold voltages when the memory system is a multi-level cell (MLC) memory system.
15. The method of claim 11 wherein the generating the training sequence includes generating the training sequence with a scrambler scrambling inputs thereof with a key or address.
16. The method of claim 11 wherein the generating the training sequence includes generating the training sequence by processing inputs of patterns.
17. The method of claim 11 wherein the writing the training sequence associated with a user data includes writing the training sequence in front of, in the middle of, or after the associated user data therewith.
18. The method of claim 11 wherein the analyzing the training sequence includes comparing the sequence read out from the memory device with the training sequence generated by the sequence generator.
19. The method of claim 11 wherein the identifying the optimal threshold voltage includes identifying at least one threshold voltage to be adjusted and applying an appropriate voltage amount thereto.
20. The method of claim 19 wherein the identifying the optimal threshold voltage includes conducting at least one identifying and adjusting iterations until reaching desired results.