Microprocessor fault detection and response system

1. A microprocessor fault detection and response system, comprising:

a microprocessor configured to operate in an normal mode and a safe mode; and

a hardware-based fault-attack aware microprocessor extension (FAME) coupled to the microprocessor, the hardware-based FAME configured to:

detect a fault injection on the microprocessor when the microprocessor operates in the normal mode to execute one or more instructions in an instruction datapath based on a clock signal having repeating clock cycles;

store fault recovery information in a fault recovery register (FRR);

switch the microprocessor from the normal mode to the safe mode; and

instruct the microprocessor to invoke a software-based trap handler in the safe mode;

wherein the software-based trap handler is configured to:

retrieve the fault recovery information from the FRR; and

restore the microprocessor to a fault-free state based on the fault recovery information.

2. The microprocessor fault detection and response system of claim 1 , wherein the software-based trap handler is further configured to apply a user-defined fault response policy upon restoring the microprocessor to the fault-free state.

3. The microprocessor fault detection and response system of claim 1 , wherein the hardware-based FAME is further configured to switch the microprocessor from the safe mode to the normal mode in response to the software-based trap handler restoring the microprocessor to the fault-free state.

4. The microprocessor fault detection and response system of claim 1 , further comprising a pipeline register, a first shadow register, and a second shadow register, wherein:

the pipeline register is configured to store a current state of the microprocessor;

the first shadow register and the second shadow register are configured to alternately store the current state and a previous state of the microprocessor in the repeating clock cycles; and

the hardware-based FAME is further configured to select a shadow register storing the previous state of the microprocessor among the first shadow register and the second shadow register to function as the FRR.

5. The microprocessor fault detection and response system of claim 1 , further comprising a pipeline register and a shadow register, wherein:

the pipeline register is configured to store a current state of the microprocessor;

the shadow register is configured to store a previous state of the microprocessor; and

the hardware-based FAME is further configured to select the shadow register to function as the FRR.

6. The microprocessor fault detection and response system of claim 1 , wherein the hardware-based FAME comprises:

a hardware-based fault detection unit (FDU) configured to detect the fault injection on the microprocessor when the microprocessor operates in the normal mode; and

a hardware-based fault control unit (FCU) configured to:

store the fault recovery information in the FRR;

switch the microprocessor from the normal mode to the safe mode; and

instruct the microprocessor to invoke the software-based trap handler in the safe mode.

7. The microprocessor fault detection and response system of claim 6 , wherein the hardware-based FCU is further configured to switch the microprocessor from the safe mode to the normal mode in response to the software-based trap handler restoring the microprocessor to the fault-free state.

8. The microprocessor fault detection and response system of claim 6 , wherein:

the hardware-based FDU is further configured to detect a back-to-back fault injection while the microprocessor operates in the safe mode; and

the hardware-based FCU is further configured to instruct the microprocessor to re-invoke the software-based trap handler in response to the hardware-based FDU detecting the back-to-back fault injection in the safe mode.

9. The microprocessor fault detection and response system of claim 8 , wherein the hardware-based FCU is further configured to reset the microprocessor in response to the hardware-based FDU detecting the back-to-back fault injection in the safe mode.

10. The microprocessor fault detection and response system of claim 6 , wherein:

the fault injection causes a clock glitch causing a shortened clock cycle among the repeating clock cycles of the clock signal; and

the hardware-based FDU is further configured to detect the fault injection in a clock cycle immediately succeeding the shortened clock cycle among the repeating clock cycles.

11. The microprocessor fault detection and response system of claim 6 , wherein:

the hardware-based FDU is further configured to generate an alarm signal in response to detecting the fault injection; and

the hardware-based FCU is further configured to:

receive and acknowledge the alarm signal generated by the hardware-based FDU;

store the fault recovery information in the FRR;

annul the one or more instructions being executed by the microprocessor in the instruction datapath;

disable write operation to the FRR;

switch the microprocessor from the normal mode to the safe mode; and

invoke the software-based trap handler to execute on the microprocessor in the safe mode.

12. The microprocessor fault detection and response system of claim 11 , wherein:

the instruction datapath of the microprocessor comprises a fetch stage, a decode stage, a register access stage, an execute stage, a memory stage, an exception stage, and a write-back stage;

the hardware-based FDU is further configured to generate the alarm signal prior to the exception stage; and

the hardware-based FCU is further configured to invoke the software-based trap handler prior to the write-back stage.

13. The microprocessor fault detection and response system of claim 12 , wherein the fault recovery information stored in the FRR comprises a return address to an interrupted user application, a status register of the microprocessor, and a register file input of the write-back stage.

14. A method for protecting a microprocessor from fault injections, comprising:

detecting a fault injection on a microprocessor when the microprocessor operates in a normal mode to execute one or more instructions in an instruction datapath based on a clock signal having repeating clock cycles;

storing fault recovery information in a fault recovery register (FRR);

switching the microprocessor from the normal mode to a safe mode;

instructing the microprocessor to invoke a software-based trap handler in the safe mode;

retrieving the fault recovery information from the FRR by the software-based trap handler;

restoring the microprocessor to a fault-free state based on the fault recovery information;

detecting a back-to-back fault injection while the microprocessor operates in the safe mode; and

instructing the microprocessor to re-invoke the software-based trap handler in response to detecting the back-to-back fault injection in the safe mode.

15. The method of claim 14 , further comprising applying a user-defined fault response policy upon restoring the microprocessor to the fault-free state.

16. The method of claim 14 , further comprising switching the microprocessor from the safe mode to the normal mode in response to restoring the microprocessor to the fault-free state.

17. The method of claim 14 , further comprising:

storing a current state of the microprocessor in a pipeline register;

alternately storing the current state and a previous state of the microprocessor in a first shadow register and a second shadow register in the repeating clock cycles; and

selecting a shadow register storing the previous state of the microprocessor among the first shadow register and the second shadow register to function as the FRR.

18. The method of claim 14 , further comprising:

storing a current state of the microprocessor in a pipeline register;

storing a previous state of the microprocessor in a shadow register; and

selecting the shadow register to function as the FRR.

19. The method of claim 14 , further comprising resetting the microprocessor in response to detecting the back-to-back fault injection in the safe mode.