Variable gain amplifiers for communication systems
The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.
1. A variable-gain amplifier device comprising:
an equalizer section comprising:
a first transistor and a second transistor, the first transistor comprising a first gate terminal coupled to a first input signal and a first drain terminal coupled to a first output node, the second transistor comprising a second gate terminal coupled to a second input signal and a second drain terminal coupled to a second output node;
a first common mode resistor coupled to the first output node;
a second common mode resistor coupled to the second output node and the first common mode resistor;
a digital-to-analog (DAC) configured to generate a control voltage based a gain control code;
an amplifier section comprising:
a third transistor and a fourth transistor, the third transistor comprising a third gate terminal coupled to the first output node and a third drain node coupled to a third output node, the fourth transistor comprising a fourth gate terminal coupled to the second output node and a fourth drain terminal coupled to a third output node; and
a fifth transistor comprising a fifth gate terminal coupled to the control voltage and common node between the first common mode resistor and the second common resistor, the fifth transistor being characterized by a resistance value configured between source terminals of the third transistor and the fourth transistor, the resistance value being adjustable using the control voltage.
2. The device of claim 1 further comprising:
a first load resistor coupled to the first output node;
a second load resistor coupled to the second output node.
3. The device of claim 2 further comprising a current source coupled to a source terminal of the first input transistor.
4. The device of claim 2 further comprising a voltage supply coupled to the first resistor.
5. The device of claim 1 further comprising:
a first load capacitor coupled to the third output node;
a second load capacitor coupled to the fourth output node.
6. The device of claim 1 wherein a sum of a common voltage and the control voltage is greater than a threshold voltage of the fifth transistor.
7. The device of claim 6 wherein the fifth transistor comprises a triode region transistor.
8. The device of claim 6 wherein the threshold voltage is associated with a gate-source voltage differential.
9. The device of claim 1 wherein the gain control code is calibrated based at least on a voltage of the common node.
10. The device of claim 9 wherein resistance value is substantially linear relative to the gain control code.
11. A variable gain amplifier device comprising:
a first transistor and a second transistor, the first transistor comprising a first gate terminal coupled to a first input signal and a first drain terminal coupled to a first output node, the second transistor comprising a second gate terminal coupled to a second input signal and a second drain terminal coupled to a second output node;
a first common mode resistor coupled to the first output node;
a second common mode resistor coupled to the second output node and the first common mode resistor;
a first load resistor coupled to the first output node;
a digital-to-analog (DAC) configured to generate a control voltage based a gain control code;
a third transistor and a fourth transistor, the third transistor comprising a third gate terminal coupled to the first output node and a third drain node coupled to a third output node, the fourth transistor comprising a fourth gate terminal coupled to the second output node and a fourth drain terminal coupled to a third output node; and
a fifth transistor comprising a fifth gate terminal coupled to the control voltage and common node between the first common mode resistor and the second common resistor, the fifth transistor being configured to operate in a triode region and characterized by a resistance value configured between source terminals of the third transistor and the fourth transistor, the resistance value being adjustable using the control voltage.
12. The device of claim 11 wherein the first transistor comprises a PMOS transistor.
13. The device of claim 11 wherein the third transistor comprises a PMOS transistor.
14. The device of claim 11 further comprising a voltage supply coupled to the first load resistor.
15. The device of claim 11 wherein the control voltage is predetermined based on a common mode voltage and a triode region voltage associated with the fifth transistor.
16. A serializer/deserializer (SerDes) apparatus comprising:
a data communication interface for receiving a first input signal and a second input signal;
a loss of signal detection module configured for checking signal presence at the data communication interface;
a continuous-time linear equalizer (CTLE) section configured for providing a common mode voltage and a first equalized signal and a second equalized signal based at least on the first input signal and the second input signal;
a digital-to-analog (DAC) section configured for generating a control signal based on a control code;
a variable gain amplifier (VGA) section comprising a transistor and configured to generate a first amplified signal and a second amplified signal based on the first equalized signal and the second equalized signal, the VGA section being characterized by a gain ratio being based on a ratio between a load resistance and a degeneration resistance value of the transistor, the degeneration resistance value being a function of the common mode voltage and the control signal; and
a clock data recovery module being configured to generate a clock signal using at least the first equalize signal and the second equalized signal.
17. The apparatus of claim 16 wherein the clock data recovery module operates in a standby mode if the loss of signal detection module fails to detect signal presence.
18. The apparatus of claim 16 wherein the data communication interface is coupled to a wired communication lane.
19. The apparatus of claim 16 wherein data communication interface is coupled to one or more input inductors.
20. The apparatus of claim 16 wherein the data communication interface is coupled to one or more input resistors.