Gate pickup method using metal selectivity
A method of fabricating a FinFET device includes forming contact openings for source/drain contacts prior to performing a replacement metal gate (RMG) module. Etch selective metals are used to form source/drain contacts and gate contacts optionally within active device regions using a block and recess technique.
1. A method of forming a FinFET device, comprising:
forming source/drain junctions over source/drain regions of a semiconductor fin;
forming a first dielectric layer directly over the source/drain junctions;
forming a second dielectric layer laterally adjacent to the first dielectric layer and extending orthogonal to a length direction of the fin; and
forming a gate over a channel region of the semiconductor fin between the source/drain regions and adjacent to the previously-formed first and second dielectric layers, wherein the gate comprises a gate dielectric disposed over the channel region and a gate conductor disposed over the gate dielectric.
2. The method of claim 1 , wherein the first dielectric layer comprises silicon dioxide (SiO 2 ) and the second dielectric layer comprises silicon oxycarbide (SiOC).
3. The method of claim 1 , further comprising forming a sacrificial gate over the channel region of the semiconductor fin prior to forming the source/drain junctions.
4. The method of claim 3 , further comprising forming sidewall spacers over sidewalls of the sacrificial gate and a conformal liner over the sidewall spacers and over the source/drain junctions.
5. The method of claim 4 , wherein the sidewall spacers comprise SiOCN and the conformal liner comprises silicon nitride.
6. The method of claim 4 , wherein the sidewall spacer has a thickness of 4 to 20 nm and comprises silicon nitride.
7. The method of claim 4 , wherein forming the gate comprises removing the sacrificial gate selective to the sidewall spacers and the conformal liner.
8. The method of claim 1 , further comprising:
forming a first hard mask over a first portion of the gate;
recessing a second portion of the gate unblocked by the first hard mask;
forming a capping layer over the recessed second portion of the gate;
etching the first dielectric layer and the conformal liner to expose the source/drain junctions;
forming a contact layer over the source/drain junctions;
forming a second hard mask over a first portion of the contact layer;
recessing a second portion of the contact layer unblocked by the second hard mask; and
forming a capping layer over the recessed second portion of the contact layer.
9. The method of claim 8 , wherein the first portions of the gate and the first portions of the contact layer are each at least partially disposed over the semiconductor fin.
10. The method of claim 8 , wherein the second portion of the contact layer is recessed using a wet etch selective to the gate.
11. The method of claim 8 , wherein the contact layer comprises cobalt and the gate comprises tungsten.