Semiconductor device with contracted isolation feature and formation method thereof
A method of forming a semiconductor device includes forming a first dummy gate structure over a substrate, forming gate spacers over the substrate, cutting the first dummy gate structure to form separated dummy gate portions, forming a dielectric feature between the dummy gate portions, and performing a thermal process to the dielectric feature to contract the dielectric feature, wherein the contraction of the dielectric feature deforms at least one of the gate spacers such that a distance between the gate spacers is increased.
1. A method of forming a semiconductor device, comprising:
forming a first dummy gate structure over a substrate;
forming gate spacers over the substrate;
cutting the first dummy gate structure to form separated dummy gate portions;
forming a dielectric feature between the dummy gate portions;
performing a thermal process to the dielectric feature to contract the dielectric feature, the contraction of the dielectric feature deforming at least one of the gate spacers such that a distance between the gate spacers is increased; and
forming a second dummy gate structure prior to performing the thermal process, wherein the contraction of the dielectric feature enlarges the second dummy gate structure.
2. The method of claim 1 , wherein the forming the dielectric feature comprises depositing a flowable dielectric material between the dummy gate portions.
3. The method of claim 2 , wherein the thermal process densifies the flowable dielectric material.
4. The method of claim 1 , further comprising:
forming a dielectric liner between the dummy gate portions prior to the forming the dielectric feature, wherein the forming the dielectric feature comprises forming the dielectric feature into a recess of the dielectric liner.
5. The method of claim 4 , wherein the dielectric feature has higher flowability than that of the dielectric liner before the performing the thermal process.
6. The method of claim 4 , wherein the dielectric liner is a silicon nitride layer.
7. The method of claim 6 , wherein the forming the dielectric feature comprises forming a flowable oxide into the recess of the silicon nitride layer.
8. The method of claim 4 , wherein the contraction of the dielectric feature deforms the dielectric liner.
9. The method of claim 4 , wherein the contraction of the dielectric feature is greater than contraction of the dielectric liner during the thermal process.
10. The method of claim 1 , further comprising:
removing the enlarged second dummy gate structure to form a gate trench between the gate spacers; and
forming a gate metal into the gate trench.
11. The method of claim 1 , further comprising forming a third dummy gate structure between the first and second dummy gate structures.
12. The method of claim 11 , further comprising replacing the third dummy gate structure with a gate metal.
13. A method of forming a semiconductor device, comprising:
forming a first dummy gate structure over a substrate;
forming gate spacers over the substrate;
forming an opening in the first dummy gate structure;
forming an isolation feature into the opening in the first dummy gate structure;
contracting the isolation feature, thereby deforming at least one of the gate spacers to increase a distance between the gate spacers;
forming a second dummy gate structure prior to contracting the isolation feature, wherein contracting the isolation feature expands the second dummy gate structure; and
replacing the expanded second dummy gate structure with a gate metal.
14. The method of claim 13 , wherein the isolation feature is formed using a flowable chemical vapor deposition process, and wherein the contracting the isolation feature comprises performing an annealing process after the flowable chemical vapor deposition process.
15. The method of claim 13 , wherein the isolation feature is a flowable oxide before the contracting.
16. The method of claim 13 , further comprising:
forming a dielectric liner lining a sidewall of the opening in the first dummy gate structure, wherein the isolation feature is filled into a recess of the dielectric liner.
17. A method of forming a semiconductor device, wherein the method comprises:
forming a plurality of fins respectively protruding from a substrate;
forming a first dummy gate structure and a second dummy gate structure crossing the fins;
forming a gate spacer adjoining a side of the second dummy gate structure;
growing source/drain devices on both sides of each of the first dummy gate structure and the second dummy gate structure on the fins;
performing a cut operation on the first dummy gate structure, thereby forming an opening;
depositing a dielectric feature in the opening;
performing a thermal operation to contract the dielectric feature, thereby deforming the gate spacer adjoining the second dummy gate structure;
removing the second dummy gate structure, thereby forming a gate trench; and
depositing a metal gate structure in the gate trench.
18. The method of claim 17 , depositing the dielectric feature in the opening further comprises:
forming a dielectric liner in the opening; and
forming a dielectric filling over the dielectric liner.
19. The method of claim 18 , wherein the dielectric filling has higher flowability than that of the dielectric liner before performing the thermal operation.
20. The method of 17 , further comprising performing the thermal operation to expand the second dummy gate structure.