Physical unclonable function for non-volatile memory
A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.
1. A method for generating a data set on an integrated circuit including a set of programmable memory cells, comprising:
exposing the set of programmable memory cells having addresses on the integrated circuit to a process inducing variant thresholds in the programmable memory cells in the set within a starting distribution of thresholds;
scanning the set of programmable memory cells to identify a first subset of the set of programmable memory cells having thresholds in a first part of the starting distribution, and a second subset of the set of programmable memory cells having thresholds in a second part of the starting distribution;
selecting the programmable memory cells using the addresses of the programmable memory cells in said at least one of the first and second subsets;
applying a biasing operation to change threshold voltages of the selected programmable memory cells to establish a changed distribution of thresholds for the set of programmable memory cells, the changed distribution having a sensing margin between the first and second subsets; and
reading the programmable memory cells in the set using a read voltage in said sensing margin.
2. The method of claim 1 , including combining the addresses of the programmable memory cells in said at least one of the first and second subsets as a function of membership in said at least one of the first and second subsets.
3. The method of claim 2 , including storing the combined addresses in a memory on the integrated circuit.
4. The method of claim 1 , wherein the programmable memory cells in the set are charge trapping memory cells, and the thresholds are threshold voltages.
5. The method of claim 1 , wherein the process inducing variant thresholds comprises etching or deposition steps during manufacturing which induce charge trapping in charge storage structures of the programmable memory cells in the set.
6. The method of claim 1 , wherein the process inducing variant thresholds comprises biasing operations using biasing circuits on the integrated circuit that induce charges in charge storage structures of the programmable memory cells in the set.
7. A method of manufacturing an integrated circuit, comprising:
forming a plurality of programmable memory cells on the integrated circuit;
connecting the integrated circuit to a system configured to exchange signals with the integrated circuit; and
using the system to generate a data set in a set of programmable memory cells in the plurality of programmable memory cells having a starting distribution of thresholds, by:
scanning the set of programmable memory cells to identify a first subset of the set of programmable memory cells having thresholds in a first part of the starting distribution, and a second subset of the set of programmable memory cells having thresholds in a second part of the starting distribution;
selecting the programmable memory cells using the addresses of the programmable memory cells in said at least one of the first and second subsets;
applying a biasing operation to change threshold voltages of the selected programmable memory cells to establish a changed distribution of thresholds for the set of programmable memory cells, the changed distribution having a sensing margin between the first and second subsets; and
reading the programmable memory cells in the set using a read voltage in said sensing margin.
8. The method of claim 7 , including combining the addresses of the programmable memory cells in said at least one of the first and second subsets as a function of membership in said at least one of the first and second subsets, and using the combined addresses as the data set.
9. The method of claim 7 , including storing the data set in a memory on the system.
10. The method of claim 7 , wherein the programmable memory cells in the set are charge trapping memory cells, and the thresholds are threshold voltages.
11. The method of claim 7 , wherein said forming includes etching or deposition steps during manufacturing which induce charge trapping in charge storage structures of the programmable memory cells in the set; and said starting distribution is an initial distribution before using circuits on the integrated circuit to apply biasing operations to induce charge tunneling.
12. The method of claim 7 , including applying an initializing biasing operation in common to the programmable memory cells in the set using circuits on the integrated circuit that induce charges in charge storage structures of the programmable memory cells in the set, and said starting distribution is a result of the initializing biasing operation.
13. An apparatus, comprising:
a set of programmable memory cells on an integrated circuit;
logic to generate a data set using the set of programmable memory cells, wherein the set of programmable memory cells has a starting distribution of thresholds, by:
scanning the set of programmable memory cells to identify a first subset of the set of programmable memory cells having thresholds in a first part of the starting distribution, and a second subset of the set of programmable memory cells having thresholds in a second part of the starting distribution;
selecting the programmable memory cells using the addresses of the programmable memory cells in said at least one of the first and second subsets;
applying a biasing operation to change threshold voltages of the selected programmable memory cells to establish a changed distribution of thresholds for the set of programmable memory cells, the changed distribution having a sensing margin between the first and second subsets; and
reading the programmable memory cells in the set using a read voltage in said sensing margin.
14. The apparatus of claim 13 , wherein said using the addresses includes:
combining the addresses of the programmable memory cells in said at least one of the first and second subsets as a function of membership in said at least one of the first and second subsets; and
using the combined addresses as the data set.
15. The apparatus of claim 13 , including storing the data set in a memory different than the set of programmable memory cells.
16. The apparatus of claim 13 , wherein the programmable memory cells in the set are charge trapping memory cells, and the thresholds are threshold voltages.
17. The apparatus of claim 13 , wherein said starting distribution is an initial distribution before using circuits on the integrated circuit to apply biasing operations to induce charge tunneling in the set of programmable memory cells.
18. The apparatus of claim 13 , including circuitry to apply an initializing biasing operation in common to the programmable memory cells in the set that induce charges in charge storage structures of the programmable memory cells in the set, and said starting distribution is a result of the initializing biasing operation.
19. The apparatus of claim 13 , wherein the logic comprises a state machine on the integrated circuit.
20. The apparatus of claim 13 , wherein the logic comprises a computer program on a system connected to the integrated circuit.
21. A product comprising:
a computer readable non-transitory data storage medium storing computer instructions for a process to generate a data set on an integrated circuit including a set of programmable memory cells, executable by a system configured to connect to the integrated circuit, the process comprising:
scanning the set of programmable memory cells to identify a first subset of the set of programmable memory cells having thresholds in a first part of a starting distribution, and a second subset of the set of the programmable memory cells having thresholds in a second part of the starting distribution;
selecting the programmable memory cells using the addresses of the programmable memory cells in said at least one of the first and second subsets;
applying a biasing operation to change threshold voltages of the selected programmable memory cells to establish a changed distribution of thresholds for the set of programmable memory cells, the changed distribution having a sensing margin between the first and second subsets; and
reading the programmable memory cells in the set using a read voltage in said sensing margin.
22. A method for generating a data set on an integrated circuit including a set of programmable memory cells, comprising:
in the set of programmable memory cells having thresholds in a starting distribution, scanning the set of programmable memory cells to identify a first subset of the set of the programmable memory cells having thresholds in a first part of the starting distribution, and a second subset of the set of the programmable memory cells having thresholds in a second part of the starting distribution;
applying a biasing operation to change thresholds of memory cells in the starting distribution to establish a sensing margin between the first and second subsets; and
providing the data set using the sensing margin.