Optimization of loops and data flow sections in multi-core processor environment
The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
1. A method for executing code on a processor, wherein the method comprises:
detecting in program code to be executed by the processor, loop code in source code accessible to the processor,
the loop code implementing one or more execution loops of the source code,
wherein the processor includes at least one execution unit comprising an array of arithmetic data processing units communicatively connected to a register file;
partitioning the loop code into a plurality of partitions by the processor, wherein the partitioning is based on arithmetic data processing resources available on the processor;
mapping, by the processor, each of the plurality of partitions, as a whole, onto a respective execution unit of the at least one execution unit; and
executing, by the processor, the plurality of partitions using the at least one execution unit, wherein execution of a respective partition is performed after the mapping of that partition.
2. The method of claim 1 wherein a group of the plurality of partitions comprises a sequence of multiple partitions, wherein the multiple partitions are mapped and executed sequentially using the at least one execution unit.
3. The method of claim 1 wherein multiple partitions of the plurality of partitions are mapped and executed in parallel using the at least one execution unit.
4. The method of claim 1 wherein at least some of the plurality of partitions include a list of required resources according to which processor resources of the processor are allocated.
5. The method of claim 1 wherein the arithmetic data processing resources include at least one of:
an amount of available arithmetic data processing units of the array of arithmetic data processing units; or
an amount of available registers of the register file.
6. The method of claim 1 wherein the plurality of partitions are defined and managed by the processor executing the plurality of partitions.
7. The method of claim 1 wherein the plurality of partitions are scheduled by a hardware scheduler in the processor executing the plurality of partitions.
8. The method of claim 1 wherein the processor further comprises a hardware instance controlling fetching, loading and starting of the plurality of partitions.
9. The method of claim 1 wherein the at least one execution unit includes a plurality of execution units, and wherein the processor further comprises a bus system connecting multiple partitions executed on different execution units of the plurality of execution units.
10. The method of claim 9 wherein the bus system is configured according to data transmission requirements between the plurality of partitions.
11. The method of claim 1 wherein the processor further comprises a programmable sequencer in hardware controlling the plurality of partitions.
12. A microprocessor on a chip comprising:
at least one execution unit comprising an array of arithmetic data processing units;
a register file comprising a plurality of data registers communicatively connected to the plurality of arithmetic processing units; and
an instruction fetcher and instruction decoder supplying instructions of one or more software threads to the plurality of arithmetic units,
wherein the microprocessor is capable of performing operations comprising:
detecting in program code to be executed by the microprocessor, loop code in source code accessible to the microprocessor,
the loop code implementing one or more execution loops of the source code;
partitioning the loop code into a plurality of partitions, wherein the partitioning is based on arithmetic data processing resources available on the microprocessor;
mapping each of the plurality of partitions, as a whole, onto a respective execution unit of the at least one execution unit; and
executing the plurality of partitions using the at least one execution unit, wherein execution of a respective partition is performed after the mapping of that partition.
13. The microprocessor according to claim 12 , wherein at least some of the plurality of partitions include a list of required resources according to which microprocessor resources of the microprocessor are allocated.
14. The microprocessor according to claim 12 , wherein the arithmetic data processing resources include at least one of:
an amount of available arithmetic data processing units of the array of arithmetic data processing units; or
an amount of available registers of the register file.
15. The microprocessor according to claim 12 , wherein the plurality of partitions are defined and managed by the processor executing the plurality of partitions.
16. The microprocessor according to claim 12 , wherein the plurality of partitions are scheduled by a hardware scheduler in the processor executing the plurality of partitions.
17. The microprocessor according to claim 12 , further comprising a hardware instance controlling fetching, loading and starting of the plurality of partitions.
18. The microprocessor according to claim 12 , wherein the at least one execution unit includes a plurality of execution units, and wherein the processor further comprises a bus system connecting multiple partitions executed on different execution units of the plurality of execution units.
19. The microprocessor according to claim 12 , wherein the bus system is configured according to data transmission requirements between the plurality of partitions.
20. The microprocessor according to claim 12 , further comprising a programmable sequencer in hardware controlling the plurality of partitions.