Semiconductor heterostructure with at least one stress control layer

1. A semiconductor heterostructure, comprising:

a substrate;

a plurality of semiconductor layers located on the substrate; and

at least one stress control layer located within the plurality of semiconductor layers, each of the at least one stress control layer inducing one of: a tensile stress or a compressive stress, in an adjacent semiconductor layer in the plurality of semiconductor layers, the induced stress changing a stress in the adjacent semiconductor layer by at least 10% as compared to a semiconductor heterostructure having no stress control layer, the change in stress of the adjacent semiconductor layer extending from a boundary with the stress control layer into an interior portion of the adjacent semiconductor layer that is at least twice a thickness of the stress control layer, wherein each at least one stress control layer includes a plurality of stress control regions, each stress control region separated from adjacent stress control regions by a predetermined spacing, each stress control region having a characteristic size that is approximately equivalent to one of: a square root of an inverse dislocation density in the adjacent semiconductor layer or a distance resulting in a critical strain within the adjacent semiconductor layer;

wherein some of the plurality of stress control regions in the at least one stress control layer extend into adjacent semiconductor layers of the plurality of semiconductor layers,

wherein some of the plurality of stress control regions that extend into adjacent semiconductor layers form a void region in those adjacent semiconductor layers, and

wherein some of the plurality of stress control regions that extend into adjacent semiconductor layers include a surface roughness extending from a portion of the stress control region in the stress control layer to a portion of the stress control region extending into the adjacent semiconductor layers.

2. The semiconductor heterostructure of claim 1 , wherein the at least one stress control layer includes at least two stress control layers, wherein each of the at least two stress control layers is formed in a different semiconductor layer.

3. The semiconductor heterostructure of claim 1 , wherein the plurality of stress control regions in the at least one stress control layer vary in one of height, material or size.

4. The semiconductor heterostructure of claim 1 , wherein the at least one stress control layer comprises stacks of stress control regions.

5. The semiconductor heterostructure of claim 1 , wherein the stress control layer includes a laminate structure of a plurality of laminate layers, each laminate layer comprising a plurality of segmented stress control regions, the segmented stress control regions in each laminate layer formed of a different material than a material of the other of the plurality of laminate layers.

6. The semiconductor heterostructure of claim 1 , wherein the plurality of stress control regions are disposed in the stress control layer in a lateral direction and a vertical direction.

7. The semiconductor heterostructure of claim 6 , wherein sets of stress control regions in each of the lateral direction and the vertical direction form a plurality of grouped domains, each grouped domain disunited from other grouped domains in the stress control layer.

8. The semiconductor heterostructure of claim 7 , wherein the set of stress control regions in each grouped domain differ in at least one of: thickness, shape, number, area, or size, from the set of stress control regions in other disunited domains.

9. An optoelectronic device, comprising:

a substrate;

a semiconductor heterostructure located on the substrate, the semiconductor heterostructure including plurality of semiconductor layers located on the substrate, the plurality of semiconductor layers including a stress control layer and an adjacent semiconductor layer, the stress control layer including a patterned layer having a plurality of elevated regions with flat depressions formed between each of the elevated regions, wherein the adjacent semiconductor layer is located over the elevated regions and in between the flat depressions, the stress control layer inducing one of: a tensile stress or a compressive stress, in the adjacent semiconductor layer, the induced stress changing a stress in the adjacent semiconductor layer by at least 10% as compared to a semiconductor heterostructure having no stress control layer, the change in stress of the adjacent semiconductor layer extending from a boundary with the stress control layer into an interior portion of the adjacent semiconductor layer that is at least twice a thickness of the stress control layer, and wherein each elevated region has a characteristic size that is approximately equivalent to one of: a square root of an inverse dislocation density in the adjacent semiconductor layer or a distance resulting in a critical strain within the adjacent semiconductor layer;

an n-type metallic contact formed on the semiconductor heterostructure;

a p-type metallic contact formed on the semiconductor heterostructure;

an n-type stress control layer formed on the n-type metallic contact, the n-type stress control layer having a plurality of n-type stress control protrusions that penetrate through the n-type metallic contact into the semiconductor heterostructure; and

a p-type stress control layer formed on the p-type metallic contact, the p-type stress control layer having a plurality of p-type stress control protrusions that penetrate through the p-type metallic contact into the semiconductor heterostructure.

10. The optoelectronic device of claim 9 , wherein the stress control layer includes one of: a patterned polycrystalline material or a patterned amorphous group III nitride semiconductor material.

11. The optoelectronic device of claim 9 , wherein the semiconductor heterostructure includes at least two stress control layers, wherein each of the at least two stress control layers is formed in a different semiconductor layer.

12. The optoelectronic device of claim 9 , wherein the elevated regions of the stress control layer are nano-pillars.

13. The optoelectronic device of claim 12 , wherein some of the nano-pillars extend beyond the adjacent semiconductor layer into another semiconductor layer of the plurality of semiconductor layers.

14. The optoelectronic device of claim 13 , wherein some of the nano-pillars extend upward above the stress control layer and some of the nano-pillars extend downward under the stress control layer.

15. The optoelectronic device of claim 13 , wherein some of the nano-pillars have an outer surface with a surface roughness.

16. The semiconductor heterostructure of claim 1 , wherein each stress control layer comprises one of a dielectric layer and a semiconductor layer transparent to ultraviolet radiation.

17. The semiconductor heterostructure of claim 2 , wherein the stress control layers include different compositional material.

18. The semiconductor heterostructure of claim 1 , wherein the stress control layer comprises a coefficient of thermal expansion that is at least 10% different from a thermal coefficient of an adjacent semiconductor layer.

19. The semiconductor heterostructure of claim 1 , wherein each of the stress control regions has a characteristic width corresponding to a current spreading length of the adjacent semiconductor layer.

20. A method, comprising:

forming an optoelectronic device, the forming including:

obtaining a substrate;

forming a semiconductor heterostructure on the substrate, the semiconductor heterostructure including plurality of semiconductor layers located on the substrate, the plurality of semiconductor layers including a stress control layer and an adjacent semiconductor layer, the stress control layer including a patterned layer having a plurality of elevated regions with flat depressions formed between each of the elevated regions, wherein the adjacent semiconductor layer is located over the elevated regions and in between the flat depressions, the stress control layer inducing one of: a tensile stress or a compressive stress, in the adjacent semiconductor layer, the induced stress changing a stress in the adjacent semiconductor layer by at least 10% as compared to a semiconductor heterostructure having no stress control layer, the change in stress of the adjacent semiconductor layer extending from a boundary with the stress control layer into an interior portion of the adjacent semiconductor layer that is at least twice a thickness of the stress control layer, and wherein each elevated region has a characteristic size that is approximately equivalent to one of: a square root of an inverse dislocation density in the adjacent semiconductor layer or a distance resulting in a critical strain within the adjacent semiconductor layer;

forming an n-type metallic contact on the semiconductor heterostructure;

forming a p-type metallic contact on the semiconductor heterostructure;

forming an n-type stress control layer on the n-type metallic contact, the n-type stress control layer having a plurality of n-type stress control protrusions that penetrate through the n-type metallic contact into the semiconductor heterostructure; and

forming a p-type stress control layer on the p-type metallic contact, the p-type stress control layer having a plurality of p-type stress control protrusions that penetrate through the p-type metallic contact into the semiconductor heterostructure.