Method of manufacturing a semiconductor device and a semiconductor device
In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
1. A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method comprising:
forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer;
recessing the first sacrificial layer so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed;
forming a second sacrificial layer on the remaining layer and the exposed source/drain structure;
patterning the second sacrificial layer and the remaining layer, thereby forming an opening;
forming a dielectric layer in the opening;
after the dielectric layer is formed, removing the patterned first and second sacrificial layers to form a contact opening over the source/drain structure; and
forming a conductive layer in the contact opening.
2. The method of claim 1 , wherein:
before the first sacrificial layer is formed, a first insulating layer is formed over the source/drain structure and the isolation insulating layer,
after the first sacrificial layer is recessed, the first insulating layer covering the upper portion of the source/drain structure is exposed, and
when the contact opening is formed, the first insulating layer is also removed.
3. The method of claim 1 , wherein the first sacrificial layer is made of Si 1-x Ge x , where 0≤x≤0.4.
4. The method of claim 1 , wherein the second sacrificial layer is made of Si 1-y Ge y , where 0.6≤y≤1.
5. The method of claim 1 , further comprising, after the second sacrificial layer is patterned and before the dielectric layer is formed:
forming a second insulating layer in the opening and over the patterned second sacrificial layer.
6. The method of claim 5 , wherein the second sacrificial layer is made of a different material than the isolation insulating layer, the first insulating layer and the second insulating layer.
7. The method of claim 1 , wherein the source/drain structure includes a fin structure and one or more epitaxial layers formed on both opposing side faces and a top of the fin structure.
8. The method of claim 1 , further comprising, before the first sacrificial layer is formed, forming a metal gate structure of the FinFET.
9. The method of claim 1 , further comprising, after the contact opening is formed and before the conductive layer is formed:
forming a silicide layer over the source/drain structure.
10. The method of claim 1 , wherein the source/drain structure includes a fin structure embedded in the isolation insulating layer and one or more epitaxial layers formed on a top of the fin structure.
11. A method of forming a semiconductor device including fin field effect transistors (FinFETs), the method comprising:
forming a first sacrificial layer over a first source/drain structure of a first FinFET structure, a second source/drain structure of a second FinFET structure and an isolation insulating layer, the first source/drain structure being disposed adjacent to the second source/drain structure;
recessing the first sacrificial layer so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and upper portions of the first and second source/drain structures are exposed;
forming a second sacrificial layer on the remaining layer and the exposed first and second source/drain structures;
patterning the second sacrificial layer and the remaining layer, thereby forming an opening between the first source/drain structure and the second source/drain structure;
forming a dielectric layer in the opening;
after the dielectric layer is formed, removing the patterned first and second sacrificial layers to faint a first contact opening over the first source/drain structure and a second contact opening over the second source/drain structure; and
forming a first conductive layer in the first contact opening and a second conductive layer in the second contact opening.
12. The method of claim 11 , further comprising, after the second sacrificial layer is formed and before the mask pattern is formed:
forming a metal gate structure over at least one of the first and second FinFET structures.
13. The method of claim 12 , wherein forming the metal gate structure includes:
forming a hard mask layer over the second sacrificial layer;
removing a dummy gate structure, thereby forming a gate space;
forming metal gate structure in the gate space; and
forming a gate cap layer over the metal gate structure.
14. The method of claim 11 , wherein:
before the first sacrificial layer is formed, a first insulating layer is formed over the first and second source/drain structures and the isolation insulating layer,
after the first sacrificial layer is recessed, the first insulating layer covering the upper portions of the first and second source/drain structures is exposed, and
when the contact opening is formed, the first insulating layer is also removed.
15. The method of claim 11 , wherein the first sacrificial layer is made of Si 1-x Ge x , where 0≤x≤0.4.
16. The method of claim 11 , wherein the second sacrificial layer is made of Si 1-y Ge y , where 0.6≤y≤1.
17. The method of claim 11 , further comprising, after the second sacrificial layer is patterned and before the dielectric layer is formed:
forming a second insulating layer in the opening and over the patterned second sacrificial layer.
18. The method of claim 11 , wherein:
the source/drain structure includes a fin structure and one or more epitaxial layers formed on both opposing side faces and a top of the fin structure.
19. The method of claim 11 , further comprising, after the contact opening is formed and before the conductive layer is formed:
forming a silicide layer over the first and second source/drain structure.
20. A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method comprising:
forming a source/drain structure of a FinFET structure,
forming a first insulating layer over the source/drain structure and an upper surface of an isolation insulating layer;
forming a Ge-based layer on a part of the first insulating layer which is formed on the upper surface of an isolation insulating layer;
forming a second insulating layer on the Ge-based layer and the source/drain structure;
patterning the second insulating layer and the Ge-based layer, thereby forming an opening;
forming a dielectric layer in the opening;
after the dielectric layer is formed, removing the patterned Ge-based layer and second insulating layer to form a contact opening over the source/drain structure; and
forming a conductive layer in the contact opening,
wherein the Ge-based layer is Si 1-x Ge x , where 0≤x≤0.4.