Stacked DRAM device and method of manufacture
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
1. A memory device comprising:
multiple dynamic random access memory (DRAM) integrated circuit (IC) chips stacked in a vertical relationship, each of the multiple DRAM IC chips including
memory core circuitry, and
input/output (I/O) circuitry;
and
wherein solely one of the multiple DRAM IC chips uses a conductive path to electrically couple the memory core circuitry to the I/O circuitry.
2. The memory device according to claim 1 , wherein a first portion of the conductive path is formed in a metal layer.
3. The memory device according to claim 2 , wherein the metal layer comprises:
a redistribution layer formed during a packaging process.
4. The memory device according to claim 2 , wherein a second portion of the conductive path is formed in at least one through-silicon-via (TSV).
5. The memory device according to claim 4 , wherein:
the conductive path electrically couples the memory core circuitry to the I/O circuitry via the metal layer and the at least one TSV.
6. The memory device according to claim 1 wherein:
the I/O circuitry of solely the DRAM IC chip using the conductive path is configured to communicate with a memory controller.
7. The memory device according to claim 1 wherein:
a portion of the conductive path includes a re-driver circuit.
8. A memory module comprising:
a substrate; and
multiple memory devices mounted to the substrate, each memory device comprising
multiple dynamic random access memory (DRAM) integrated circuit (IC) chips stacked in a vertical relationship, each DRAM IC chip including
memory core circuitry, and
input/output (I/O) circuitry;
and
wherein solely one of the multiple DRAM IC chips uses a conductive path to electrically couple the memory core circuitry to the I/O circuitry.
9. The memory module according to claim 8 , wherein a first portion of the conductive path is formed in a metal layer.
10. The memory module according to claim 9 , wherein the metal layer comprises:
a redistribution layer formed during a packaging process.
11. The memory module according to claim 9 , wherein a second portion of the conductive path is formed in at least one through-silicon-via (TSV).
12. The memory module according to claim 11 , wherein:
the conductive path electrically couples the memory core circuitry to the I/O circuitry via the metal layer and the at least one TSV.
13. The memory module according to claim 1 , wherein:
the I/O circuitry of solely the DRAM IC chip using the conductive path is configured to communicate with a memory controller.
14. The memory module according to claim 1 , wherein:
a portion of the conductive path includes a re-driver circuit.
15. A memory device comprising:
multiple dynamic random access memory (DRAM) integrated circuit (IC) chips stacked in a vertical relationship, each DRAM IC chip including
memory core circuitry, and
input/output (I/O) circuitry;
and
wherein solely one of the multiple DRAM IC chips uses means for electrically coupling the memory core circuitry to the I/O circuitry.
16. The memory device according to claim 15 , wherein the means for electrically coupling comprises:
a conductive path formed in a metal layer; and
at least one through-silicon via (TSV) electrically connected to the metal layer.
17. The memory device according to claim 16 , wherein the metal layer comprises a redistribution layer formed during a packaging process.
18. The memory device according to claim 16 , further comprising power distribution conductors formed in the metal layer.
19. The memory device according to claim 16 , further comprising a test pad formed in the metal layer.
20. The memory device according to claim 16 wherein the I/O circuitry of solely the DRAM IC chip using the conductive path is configured to communicate with a memory controller.