Nitride heterojunction bipolar transistor with polarization-assisted alloy hole-doped short-period superlattice emitter or collector layers
View Patent ↗A nitride heterojunction bipolar transistor with one or more polarization-assisted alloy hole-doped short-period superlattice layers are described herein. The transistor may comprise a substrate, a sub-collector region coupled to the substrate, a collector region coupled to the sub-collector portion, a base portion region to the collector portion, and a short-period superlattice (SPSL) emitter region coupled to the base portion. The SPSL emitter includes a plurality of first emitter layers and a plurality of second emitter layers that are alternating layers that form the SPSL emitter. The first emitter layers have a lower bandgap than the second emitter layers, and the vertical transport through the SPSL emitter region occurs via quantum tunneling. Other embodiments are also described.
1. A transistor comprising:
a substrate;
a sub-collector region coupled to the substrate;
a collector region coupled to the sub-collector region;
a base region coupled to the collector region; and
a short-period superlattice (SPSL) emitter region coupled to the base region,
wherein the SPSL emitter region includes a plurality of first emitter layers and a plurality of second emitter layers,
wherein the first emitter layers and the second emitter layers are alternating layers forming the SPSL emitter region,
wherein the first emitter layers have a lower bandgap than the second emitter layers,
wherein vertical transport through the SPSL emitter region occurs via quantum tunneling,
wherein the sub-collector region is a SPSL sub-collector region that includes a plurality of first sub-collector layers and a plurality of second sub-collector layers,
wherein the first sub-collector layers and the second sub-collector layers are alternating layers forming the SPSL sub-collector region,
wherein the first sub-collector layers have a lower bandgap than the second sub-collector layers; and
wherein the collector region is a SPSL collector region that includes a plurality of first collector layers and a plurality of second collector layers,
wherein the first collector layers and the second collector layers are alternating layers forming the SPSL collector region,
wherein the first collector layers have a lower bandgap than the second collector layers,
wherein vertical transport through the SPSL sub-collector region and the SPSL collector region occurs via quantum tunneling.
2. The transistor in claim 1 , wherein the first emitter layers are more heavily doped than the second emitter layers.
3. The transistor in claim 1 , wherein an alloy composition of the first emitter layers is different than an alloy composition of the second emitter layers.
4. The transistor in claim 1 , wherein a thickness of each of the first emitter layers is different from or same as a thickness of each of the second emitter layers.
5. The transistor in claim 1 , wherein the first sub-collector layers are more heavily doped than the second sub-collector layers, and the first collector layers are more heavily doped than the second collector layers.
6. The transistor in claim 1 , wherein an alloy composition of the first sub-collector layers is different than an alloy composition of the second sub-collector layers, and wherein an alloy composition of the first collector layers is different than an alloy composition of the second collector layers.
7. The transistor in claim 1 , wherein a thickness of each of the first sub-collector layers is different from or same as a thickness of each of the second sub-collector layers, and wherein a thickness of each of the first collector layers is different from or same as a thickness of each of the second collector layers.
8. The transistor in claim 1 , wherein the transistor is a heterojunction bipolar transistor.
9. A transistor comprising:
a substrate;
a short-period superlattice (SPSL) sub-collector region coupled to the substrate,
wherein the SPSL sub-collector region includes a plurality of first sub-collector layers and a plurality of second sub-collector layers,
wherein the first sub-collector layers and the second sub-collector layers are alternating layers forming the SPSL sub-collector region,
wherein the first sub-collector layers have a lower bandgap than the second sub-collector layers;
a SPSL collector region coupled to the SPSL sub-collector region,
wherein the SPSL collector region includes a plurality of first collector layers and a plurality of second collector layers,
wherein the first collector layers and the second collector layers are alternating layers forming the SPSL collector region,
wherein the first collector layers have a lower bandgap than the second collector layers,
wherein vertical transport through the SPSL sub-collector region and the SPSL collector region occurs via quantum tunneling;
a base region coupled to the SPSL collector region; and
an emitter region coupled to the base region.
10. The transistor in claim 9 , wherein the first sub-collector layers are more heavily doped than the second sub-collector layers, and the first collector layers are more heavily doped than the second collector layers.
11. The transistor in claim 9 , wherein an alloy composition of the first sub-collector layers is different than an alloy composition of the second sub-collector layers, and wherein an alloy composition of the first collector layers is different than an alloy composition of the second collector layers.
12. The transistor in claim 9 , wherein a thickness of each of the first sub-collector layers is different from or same as a thickness of each of the second sub-collector layers, and wherein a thickness of each of the first collector layers is different from or same as a thickness of each of the second collector layers.
13. The transistor in claim 9 , wherein the transistor is a heterojunction bipolar transistor.
14. A transistor comprising:
a substrate;
a short-period superlattice (SPSL) sub-collector region coupled to the substrate,
wherein the SPSL sub-collector region includes a plurality of first sub-collector layers and a plurality of second sub-collector layers,
wherein the first sub-collector layers and the second sub-collector layers are alternating layers forming the SPSL sub-collector region,
a SPSL collector region coupled to the SPSL sub-collector region,
wherein the SPSL collector region includes a plurality of first collector layers and a plurality of second collector layers,
wherein the first collector layers and the second collector layers are alternating layers forming the SPSL collector region,
wherein vertical transport through the SPSL sub-collector region and the SPSL collector region occurs via quantum tunneling;
a base region coupled to the SPSL collector region; and
a SPSL emitter region coupled to the base region,
wherein the SPSL emitter region includes a plurality of first emitter layers and a plurality of second emitter layers,
wherein the first emitter layers and the second emitter layers are alternating layers forming the SPSL emitter region,
wherein vertical transport through the SPSL emitter region occurs via quantum tunneling.
15. The transistor in claim 14 ,
wherein an alloy composition of the first emitter layers is different than an alloy composition of the second emitter layers, and
wherein an alloy composition of the first sub-collector layers is different than an alloy composition of the second sub-collector layers, and wherein an alloy composition of the first collector layers is different than an alloy composition of the second collector layers.
16. The transistor in claim 14 ,
wherein the first emitter layers are more heavily doped than the second emitter layers, and
wherein the first sub-collector layers are more heavily doped than the second sub-collector layers, and the first collector layers are more heavily doped than the second collector layers.
17. A transistor comprising:
a substrate;
a collector region;
a base region coupled to the collector region; and
an emitter region coupled to the base region;
wherein at least a portion of at least one of the collector region or emitter region comprises a short-period-superlattice (SPSL);
wherein the SPSL includes a plurality of layer pairs, each pair comprising a first layer having a lower bandgap material than a second layer, wherein the SPSL has nearly a-thermal lateral resistivity characteristics.
18. The transistor of claim 17 , wherein at least some of the layer pairs of the SPSL are identical.
19. The transistor of claim 17 , wherein the second layer within one layer pair of the SPSL layer has a thickness of less than 1 monolayer of a crystal lattice constant.
20. The transistor of claim 17 , further comprising a sub-collector region coupled to the collector region and to the base region, wherein the collector region and the sub-collector region are SPSL.
21. The transistor of claim 17 , wherein the emitter region and the collector region are SPSL.
22. The transistor of claim 17 , wherein the doping concentration of the base region is higher than an average doping concentration of the emitter region.
23. The transistor of claim 22 , wherein a forward injection current in the transistor is higher than a backward injection current in the transistor.