IP Library › Granted Patent US 10,444,812
Granted Patent B2
US 10,444,812 · App. 15/605,154 · Granted Oct 15, 2019

Power shifting in multicore platforms by varying SMT levels

Inventors: Pradip Bose (Yorktown Heights, NY); Alper Buyuktosunoglu (White Plains, NY); Hubertus Franke (Cortlandt Manor, NY); Priyanka Tembey (Atlanta, GA); Dilma M. Da Silva (College Station, TX)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F1/3206G06F1/26G06F1/329G06F9/4893G06F9/50G06F1/3203Y02D10/24
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Quick Facts
Patent No.
US 10,444,812
App. No.
15/605,154
Granted
Oct 15, 2019
Kind
B2
Abstract

Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

Claims (30)

1. A method for managing power consumption in a multi-core microprocessor platform, the method comprising adjusting a simultaneous multithreading level in at least one of a plurality of physical cores in the multi-core processor platform in response to a power consumption level of the multi-core microprocessor platform exceeding a peak power level by:

selecting in a random sequence physical cores from which power consumption can be taken by decreasing multithreading levels while maintaining performance levels thereby decreasing power allocated to physical cores with decreased multithreading levels, and physical cores to which power can be shifted to increase multithreading levels to achieve a highest increase in performance level by increasing a number of logical cores on those physical cores; and

adjusting the simultaneous multithreading level in the selected physical cores to achieve a desired power savings and to maximize performance of the multi-core microprocessor platform in executing multi-threaded applications.

2. The method of claim 1 , wherein the step of adjusting the simultaneous multithreading level further comprises adjusting the multithreading level in a plurality of physical cores by changing the number of logical cores on each physical core.

3. The method of claim 2 , wherein changing the number of logical cores further comprises decreasing the number of logical cores on at least one physical core and increasing the number of logical cores on at least one physical core.

4. The method of claim 1 , wherein the step of adjusting the simultaneous multithreading level further comprises decreasing the number of logical cores for a plurality of physical cores in series from the random sequence until a current power consumption level is less than or equal to the peak power level.

5. The method of claim 4 , wherein:

the method further comprises monitoring the power consumption level continuously; and

repeating the serial decreasing of the number of logical cores through the plurality of physical cores in accordance with the random sequence each time the power consumption level exceeds the peak power level.

6. The method of claim 1 , wherein the method further comprises monitoring the number of currently executing instructions per second continuously for each one of the plurality of physical cores.

7. The method of claim 1 , wherein the step of adjusting the simultaneous multi-threading level in the selected physical cores comprises shifting the multi-threading level among the selected physical cores by decreasing the number of logical cores on at least one selected physical core and increasing the number of logical cores on at least one selected physical core.

8. A method for managing power consumption in a multi-core microprocessor platform executing multi-threaded applications, the method comprising adjusting a simultaneous multithreading level in at least one physical core by changing a number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding a peak power level by:

arranging multi-threaded applications and physical cores running those multi-threaded applications into a plurality of bins, each bin comprising multi-threaded applications having common speed up curves for a given change in simultaneous multithreading level and physical cores running those applications;

selecting at least one bin from the plurality of bins in order to select physical cores from which power consumption can be taken by decreasing multithreading levels while maintaining performance levels thereby decreasing power allocated to physical cores with decreased multithreading levels and physical cores to which power can be shifted to increase multithreading levels to achieve a highest increase in performance level by increasing the number of logical cores; and

adjusting simultaneous multi-threading levels for all physical cores in each selected bin.

9. A non-transitory computer-readable storage medium containing a computer-readable code that when read by a computer causes the computer to perform a method for managing power consumption in a multi-core microprocessor platform, the method comprising adjusting a simultaneous multithreading level in at least one of a plurality of physical cores in the multi-core processor platform in response to a power consumption level of the multi-core microprocessor platform exceeding a peak power level by:

selecting in a random sequence physical cores from which power consumption can be taken by decreasing multithreading levels while maintaining performance levels thereby decreasing power allocated to physical cores with decreased multithreading levels and physical cores to which power can be shifted to increase multithreading levels to achieve a highest increase in performance level by increasing a number of logical cores on those physical cores; and

adjusting the simultaneous multithreading level in the selected physical cores to achieve a desired power savings and to maximize performance of the multi-core microprocessor platform in executing multi-threaded applications.

10. The non-transitory computer-readable storage medium of claim 9 , wherein the step of adjusting the simultaneous multithreading level further comprises adjusting the multithreading level in a plurality of physical cores by changing the number of logical cores on each physical core.

11. The non-transitory computer-readable storage medium of claim 10 , wherein changing the number of logical cores further comprises decreasing the number of logical cores on at least one physical core and increasing the number of logical cores on at least one physical core.

12. The non-transitory computer-readable storage medium of claim 9 , wherein the step of adjusting the simultaneous multithreading level further comprises decreasing the number of logical cores for a plurality of physical cores in series from the random sequence until a current power consumption level is less than or equal to the peak power level.

13. The non-transitory computer-readable storage medium of claim 12 , wherein:

the method further comprises monitoring the power consumption level continuously; and

repeating the serial decreasing of the number of logical cores through the plurality of physical cores in accordance with the random sequence each time the power consumption level exceeds the peak power level.

14. The non-transitory computer-readable storage medium of claim 9 , wherein the method further comprises monitoring the number of currently executing instructions per second continuously for each one of the plurality of physical cores.

15. The non-transitory computer-readable storage medium of claim 9 , wherein the step of adjusting the simultaneous multi-threading level in the selected physical cores comprises shifting the multi-threading level among the selected physical cores by decreasing the number of logical cores on at least one selected physical core and increasing the number of logical cores on at least one selected physical core.

16. A non-transitory computer-readable storage medium containing a computer-readable code that when read by a computer causes the computer to perform a method for managing power consumption in a multi-core microprocessor platform executing multi-threaded applications, the method comprising adjusting a simultaneous multithreading level in at least one physical core by changing a number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding a peak power level by:

arranging multi-threaded applications and physical cores running those multi-threaded applications into a plurality of bins, each bin comprising multi-threaded applications having common speed up curves for a given change in simultaneous multithreading level and physical cores running those applications;

selecting at least one bin from the plurality of bins in order to select physical cores from which power consumption can be taken by decreasing multithreading levels while maintaining performance levels thereby decreasing power allocated to physical cores with decreased multithreading levels and physical cores to which power can be shifted to increase multithreading levels to achieve a highest increase in performance level by increasing the number of logical cores; and

adjusting simultaneous multi-threading levels for all physical cores in each selected bin.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2026
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: KIDON IP CORPORATION
Reel/Frame 074125/0530 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2026
From: KIDON IP CORPORATION
To: CAPROCK INTEGRATED TECHNOLOGIES LLC
Reel/Frame 073866/0504 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2026
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: KIDON IP CORPORATION
Reel/Frame 074975/0477 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2017
From: BOSE, PRADIP; BUYUKTOSUNOGLU, ALPER; FRANKE, HUBERTUS; TEMBEY, PRIYANKA; DA SILVA, DILMA M.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 042507/0905 →
Continuity (3)
Continuation 14603722 · Jan 23, 2015
Continuation 13476179 · May 21, 2012
Related Publication 20170308147A1 · Oct 26, 2017