Semiconductor element and fabrication method thereof
A semiconductor element includes a super-lattice buffer layer including Al x N 1-x layers and Al y O 1-y layers (0<x<1, 0<y<1). The super-lattice buffer layer can mitigate corrosion to the side wall by chemical solution during chip fabrication, and improve chip yield. Fabrication the super-lattice buffer layer to achieve the effects can be realized, for example, using chemical vapor deposition (CVD).
1. A semiconductor element, comprising: a substrate, a buffer layer, an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer, wherein: the buffer layer is a super-lattice structure layer with periodically-laminated Al x N 1-x layers and Al y O 1-y layers (0<x<1, 0<y<1); and a first cycle of the super-lattice structure layer, the Al y O 1-y layer is on the Al x N 1-x layer.
2. The semiconductor element according to claim 1 , wherein: number of periods in the super-lattice structure layer is ≥2.
3. The semiconductor element according to claim 1 , wherein: a thickness of the Al x N 1-x is a thickness of the Al y O 1-y layer.
4. The semiconductor element according to claim 1 , wherein: the Al x N 1-x layer and the Al y O 1-y layer each have a thickness of 5-500 Å.
5. The semiconductor element according to claim 1 , wherein: a non-doping semiconductor layer is disposed between the buffer layer and the N-type semiconductor layer.
6. A semiconductor element, comprising: a substrate, a buffer layer, an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer, wherein: the buffer layer is a super-lattice structure layer with periodically-laminated Al x N 1-x layers and Al y O 1-y layers (0<x<1, 0<y<1), wherein: the super-lattice structure layer is configured to mitigate corrosion to a side wall by chemical solution during chip fabrication and improve chip yield.
7. A light-emitting system comprising a plurality of semiconductor elements, each semiconductor element comprising: a substrate, a buffer layer, an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer, wherein: the buffer layer is a super-lattice structure layer with periodically-laminated Al x N 1-x layers and Al y O 1-y layers (0<x<1, 0<y<1); and a thickness of the Al x N 1-x is a thickness of the Al y O 1-y layer.
8. The system according to claim 7 , wherein: a first cycle of the super-lattice structure layer, the Al y O 1-y layer is on the Al x N 1-x layer.
9. The system according to claim 7 , wherein: the super-lattice structure layer is configured to mitigate corrosion to a side wall by chemical solution during chip fabrication and improve chip yield.
10. The system according to claim 7 , wherein: number of periods in the super-lattice structure layer is ≥2.
11. The system according to claim 7 , wherein: the Al x N 1-x layer and the Al y O 1-y layer each have a thickness of 5-500 Å.
12. The system according to claim 7 , wherein: a non-doping semiconductor layer is disposed between the buffer layer and the N-type semiconductor layer.
13. The system according to claim 7 , wherein each element is fabricated with a method comprising:
S1. providing a growth substrate;
S2. deposing a super-lattice buffer layer composed of periodically-laminated Al x N 1-x layers and Al y O 1-y layers (0<x<1, 0<y<1) on the substrate surface via physical vapor deposition (PVD), in which, the buffer layer can mitigate corrosion to the side wall by chemical solution in subsequent chip fabrication and improve chip yield;
S3. depositing an epitaxial layer composed of an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer on the buffer layer surface via chemical vapor deposition (CVD).
14. The system according to claim 13 , wherein: in S2, an Al x N 1-x layer is deposited on the substrate surface via PVD, and an Al y O 1-y layer is deposited on a surface of the Al x N 1-x layer, thereby forming a super-lattice buffer layer through successive and periodical lamination.
15. The system according to claim 14 , wherein: in S3, at first, a non-doping semiconductor layer is deposited on the buffer layer surface and an N-type semiconductor layer is then deposited.