Manufacturing method of semiconductor device and semiconductor device

1. A manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate, the manufacturing method of a semiconductor device comprising:

forming an n-type gallium nitride layer on a gallium nitride monocrystalline substrate having a threading dislocation density of less than 1E+7 cm −2 ; and

forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, the impurities including at least one element selected from among magnesium, beryllium, calcium and zinc, wherein

at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.

2. The manufacturing method of a semiconductor device as set forth in claim 1 , wherein

during the formation of the impurity-implanted region,

the impurities are ion-implanted into the n-type gallium nitride layer by accelerating the impurities with an energy of 10 keV or higher and 200 keV or lower depending on a depth of the impurity-implanted region and with a dosage being set to 1E+12 cm −2 or higher and 1E+14 cm −2 or lower.

3. The manufacturing method of a semiconductor device as set forth in claim 2 , wherein

the impurity-implanted region contains the impurities at a concentration of 1E+16 cm- 3 or higher and 1E+18 cm −3 or lower.

4. The manufacturing method of a semiconductor device as set forth in claim 1 , further comprising

subsequent to the formation of the n-type gallium nitride layer and prior to the formation of the impurity-implanted region, forming a high-concentration impurity region containing the impurities at a high concentration at a position deeper than the impurity-implanted region.

5. The manufacturing method of a semiconductor device as set forth in claim 4 , wherein

during the formation of the high-concentration impurity region,

the impurities are ion-implanted into the n-type gallium nitride layer by accelerating the impurities with an energy of 300 keV or higher and 800 keV or lower depending on a depth of the high-concentration impurity region and with a dosage being set to 1E+14 cm −2 or higher and 1E+15 cm −2 or lower.

6. The manufacturing method of a semiconductor device as set forth in claim 5 , wherein

the high-concentration impurity region contains the impurities at a concentration of 1E+19 cm-3 or higher and 1E+20 cm-3 or lower.

7. The manufacturing method of a semiconductor device as set forth in claim 4 , wherein

during the formation of the high-concentration impurity region,

the high-concentration impurity region containing the impurities at a concentration of 1E+18 cm-3 or higher and 1E+20 cm-3 or lower is epitaxially formed on the n-type gallium nitride layer.

8. The manufacturing method of a semiconductor device as set forth in claim 1 , wherein

the impurities are magnesium.

9. The manufacturing method of a semiconductor device as set forth in claim 1 , further comprising:

subsequent to the formation of the impurity-implanted region, forming a cap layer on the impurity-implanted region, the cap layer being in direct contact with the impurity-implanted region; and

subsequent to the formation of the cap layer, performing annealing on the impurity-implanted region at a temperature of 1100° C. or higher and 1400° C. or lower.

10. The manufacturing method of a semiconductor device as set forth in claim 1 , wherein:

the n-type gallium nitride layer is not subjected to etching, and

concentration distribution of the impurities in the impurity-implanted region in the n-type gallium nitride layer is regulated by the ion-implantation in place of thermal diffusion.