IP Library Granted Patent US 10,186,502
Granted Patent B1
US 10,186,502 · App. 15/607,915 · Granted Jan 22, 2019

Integrated circuit having a component provided by transfer print and method for making the integrated circuit

Inventor: Ralf Lerner (Erfurt, DE)
Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
H01L25/18H01L21/6835H01L23/367H01L23/528H01L23/5226H01L23/5389H01L24/19H01L24/24H01L25/50H01L2221/68354H01L2221/68368H01L2221/68377H01L2224/24147H01L2224/82005
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,186,502
App. No.
15/607,915
Granted
Jan 22, 2019
Kind
B1
Abstract

A component to be transferred to a receiving substrate is to be coupled both electrically and thermally. This is achieved by an integrated circuit comprising a substrate and a plurality of first components formed in or on the substrate. A plurality of metallization layers are provided. A second component applied by transfer printing is provided which is positioned, at least in part, on a level with and laterally adjacent to at least one of the plurality of metallization layers.

Claims (38)

1. An integrated circuit including a substrate, comprising:

a plurality of first components formed at least one of in and on the substrate with a first metallization layer connected by contacts to said plurality of first components and with a second metallization layer connected by first vias to said first metallization layer;

a plurality of metallization layers;

a second component applied by transfer printing, the second component positioned, at least in part, on a level with and laterally adjacent to at least one of the plurality of metallization layers.

2. The integrated circuit according to claim 1 , wherein a metal-containing area is provided beneath the second component ( 20 ) and between the second component and the substrate.

3. The integrated circuit according to claim 2 , wherein the metal-containing area is a part of at least one or more of the plurality of metallization layers.

4. The integrated circuit according to claim 3 , wherein the metal-containing area comprises a plurality of one or more contacts and vias.

5. The integrated circuit according to claim 2 , wherein the metal-containing area comprises a plurality of one or more contacts and vias.

6. The integrated circuit according to claim 2 , wherein the metal-containing area is formed as an extensive contact.

7. The integrated circuit according to claim 1 , wherein the second component rests on a lowered portion of a dielectric layer.

8. The integrated circuit according to claim 7 , wherein a non-lowered portion of the dielectric layer functions as an insulation layer, or as a part thereof, for one of the plurality of metallization layers.

9. The integrated circuit according to claim 1 , wherein a metallization layer is arranged above the second component.

10. The integrated circuit according to claim 9 , wherein the metallization layer arranged above the second component comprises at least one contact which is connected to the second component.

11. The integrated circuit according to claim 10 , wherein the metallization layer arranged above the second component comprises a plurality of contacts which are connected to the second component.

12. The integrated circuit according to claim 3 , wherein the metal-containing area is a part of the plurality of metallization layers.

13. An integrated circuit including a substrate, comprising:

a plurality of first components formed in or on the substrate;

a plurality of metallization layers;

a second component applied by transfer printing which is positioned, at least in part, on a level with and laterally adjacent to at least one of the plurality of metallization layers, the second component applied by transfer printing comprising at least one laterally protruding residue of a connection element which retained the component before release thereof.

14. An integrated circuit including a substrate, comprising:

a plurality of first components formed in or on the substrate;

a plurality of metallization layers;

one or more second components, which are lifted, separated, moved and disposed in a new location, at least in part, on a level with and laterally adjacent to at least one of the plurality of metallization layers by printing via transfer print using one or more connection elements which retained the component before separation thereof, each of the one or more second components comprises at least one laterally protruding residue of a connection element thereof.

15. The integrated circuit according to claim 14 , wherein each component comprises a plurality of respective laterally protruding residues of its connection elements.

16. A method for producing an integrated circuit, the method comprising the following steps:

forming a pit in at least one metallization layer, wherein the pit extends up to a metal-containing area, or a buried dielectric layer located above a conductive substrate area;

forming a dielectric layer in the pit and above the at least one metallization layer;

arranging a component in the pit on the dielectric layer by transfer printing comprising a releasing, a transferring, and a printing.

17. The method according to claim 16 , comprising forming at least one further metallization layer above the component, and connecting the component to the at least one further metallization layer.

18. The method according to claim 16 , wherein the metal-containing area or the buried dielectric layer is used as an etching stop layer.

19. The method according to claim 16 , wherein the metal-containing area is formed in the production of a lower metallization layer produced prior to the at least one metallization layer, or in the production of contacts or vias beneath the lower metallization layer.

20. The method according to claim 19 , wherein the metal area is formed within the scope of production of a metal layer located further below and thus produced in an earlier stage.

21. The method according to claim 16 , wherein a depth of the pit is adjusted to a height dimension of the component such that a projection of the component is less than 20 μm after arrangement thereof in the pit.

22. The method according to claim 21 , wherein the projection is less than 5 μm.

23. The method according to claim 21 , wherein adjustment of the depth of the pit to the height dimension of the component is performed via a number of metallization layers produced prior to forming the pit.

24. The method according to claim 16 , wherein the second component applied by transfer printing comprises at least one laterally protruding residue of a connection element which retained the component before release thereof.

25. The method according to claim 16 , wherein one or more components, which are lifted, separated, moved and disposed in a new location by printing via transfer print, each component comprises at least one laterally protruding residue of a connection element.

26. The method according to claim 25 , wherein each component, which is arranged in the pit on the dielectric layer by transfer printing, comprising releasing, transferring, and printing, and each component comprises a plurality of respective laterally protruding residues of its connection elements thereof.

Assignments (2)
CHANGE OF NAME Recorded Jul 23, 2019
From: X-FAB SEMICONDUCTOR FOUNDRIES AG
To: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
Reel/Frame 049841/0497 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2017
From: LERNER, RALF
To: X-FAB SEMICONDUCTOR FOUNDRIES AG
Reel/Frame 043201/0985 →
Priority Claims (1)
DE 10 2016 109 950 · May 30, 2016 · national
Cited By (1)
US 12,322,672