Method and apparatus for en route translation in solid state graphics systems
Described herein is a method and apparatus for en route translation of data by a data translation logic (DTL) on a solid state graphics (SSG) device as the data moves from a first memory architecture on the SSG device to a second memory architecture associated with a graphics processing units (GPU) on the SSG device or from the first memory architecture on the SSG device to a host memory in a host system that is connected to the SSG device.
1. A solid state graphics (SSG) device, comprising:
at least one first memory architecture and an associated first memory architecture controller;
at least one graphics processing unit (GPU);
a second memory architecture associated with each GPU;
a data translator; and
an expansion bus interface connected to each associated first memory architecture controller, the at least one GPU, and the data translator,
wherein the data translator:
en route detects a data form of data read from the at least one first memory architecture in response to a data transfer command and received at the data translator via the associated first memory architecture controller and expansion bus interface;
en route determines if read data is in clear form for a target device;
en route applies data processing to the read data to generate clear data with respect to the target device when the read data is not in clear form; and
transfers the clear data to a target memory associated with the target device.
2. The SSG device of claim 1 , wherein the target device is the at least one GPU.
3. The SSG device of claim 2 , wherein the target memory is the second memory architecture.
4. The SSG device of claim 3 , wherein the second memory architecture is local memory and the at least one first memory architecture is a non-volatile memory.
5. The SSG device of claim 3 , wherein the data transfer command is sent by the at least one GPU.
6. The SSG device of claim 1 , wherein the expansion bus interface is connected to a host processing system including a processor connected to a host memory and the target device is the processor.
7. The SSG device of claim 6 , wherein the target memory is the host memory.
8. The SSG device of claim 7 , wherein the data transfer command is sent by the processor.
9. The SSG device of claim 8 , wherein the at least one first memory architecture is a non-volatile memory.
10. The SSG device of claim 2 , wherein the expansion bus interface is connected to a host processing system including a processor and the data transfer command is sent by the processor.
11. A method for transferring data, the method comprising:
receiving, at a data translator via at least an expansion bus interface, data read from at least one first memory architecture in response to a data transfer command from a requesting device, wherein the data translator, the expansion bus interface and the at least one first memory architecture are part of a solid state graphics (SSG) device;
en route detecting, by the data translator, a data form of read data;
en route determining, by the data translator, if the read data is in clear form for a target device;
en route applying, by a data translator, data processing to the read data to generate clear data with respect to the target device when the read data is not in clear form; and
transferring, by the data translator, the clear data to a target memory.
12. The method of claim 11 , wherein the target device is at least one graphics processing unit (GPU) and the at least one GPU is part of the SSG device.
13. The method of claim 12 , wherein the target memory is a second memory architecture associated with the at least one GPU and the second memory architecture is part of the SSG device.
14. The method of claim 13 , wherein the second memory architecture is local memory and the at least one first memory architecture is a non-volatile memory.
15. The method of claim 14 , wherein the requesting device is the at least one GPU.
16. The method of claim 14 , wherein the expansion bus interface is connected to a host processing system that includes a processor and the requesting device is a processor.
17. The method of claim 11 , wherein the expansion bus interface is connected to a host processing system that includes a processor and a host memory and the target device is the processor.
18. The method of claim 17 , wherein the target memory is the host memory.
19. The method of claim 18 , wherein the requesting device is the processor.
20. The method of claim 18 , wherein the at least one first memory architecture is a non-volatile memory.