CARRIERLESS CHIP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME
Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.
1 . A device, comprising:
a body of encapsulant material having a lowermost surface;
a integrated circuit chip having a first surface on which are disposed a plurality of bond pads, a second surface opposite the first surface, and one or more sides, the first surface and the one or more sides being encapsulated by the body of encapsulant material, the second surface being exposed and coplanar with the lowermost surface of the body of encapsulant material;
a plurality of conductive portions disposed in the body of encapsulant material, each of the plurality of conductive portions having an exposed lower surface coplanar with the lowermost surface of the body of encapsulant material; and
a plurality of conductive members disposed in the body of encapsulant material, each of the plurality of conductive members coupling corresponding ones of the plurality of bond pads and the plurality of conductive portions.
2 . The device of claim 1 , further comprising a conductive structure that is conductively coupled to one or more of the plurality of conductive portions.
3 . The device of claim 2 , wherein the integrated circuit chip is conductively coupled to the conductive structure by a plurality of solder joints.
4 . The device of claim 1 , wherein the plurality of conductive portions are disposed peripherally around the second surface of the integrated circuit chip.
5 . The device of claim 1 , further comprising a plurality of conductive features coupled to the lower surfaces of the plurality of conductive portions.
6 . The device of claim 1 , wherein the plurality of conductive members are completely encapsulated by the body of encapsulant material.
7 . The device of claim 1 , wherein the integrated circuit chip comprises at least one of a memory device, a microprocessor and an application specific integrated circuit device.
8 . The device of claim 1 , wherein the plurality of conductive members are comprised of one or more of gold, aluminum and copper.
9 . The device of claim 1 , wherein the plurality of conductive portions are comprised of aluminum.
10 . The device of claim 1 , wherein the body of encapsulant material comprises an epoxy compound or a molding compound.
11 . A device, comprising:
a body of encapsulant material having a lowermost surface;
a integrated circuit chip having a first surface, a plurality of bond pads, a second surface opposite the first surface, and one or more sides, the first surface and the one or more sides being encapsulated by the body of encapsulant material, the second surface being exposed and coplanar with the lowermost surface of the body of encapsulant material;
a plurality of conductive portions disposed in the body of encapsulant material, each of the plurality of conductive portions having an exposed lower surface coplanar with the lowermost surface of the body of encapsulant material; and
a plurality of wirebonds disposed in the body of encapsulant material, each of the plurality of wirebonds coupling corresponding ones of the plurality of bond pads and the plurality of conductive portions.
12 . The device of claim 11 , wherein the plurality of bond pads are disposed on the first surface of the integrated circuit chip.
13 . The device of claim 11 , wherein the plurality of conductive portions have a cross-sectional area greater than an average cross-sectional area of the plurality of wirebonds.
14 . The device of claim 11 , wherein the plurality of conductive portions are disposed peripherally around the second surface of the integrated circuit chip.
15 . The device of claim 11 , further comprising a plurality of conductive features coupled to the lower surfaces of the plurality of conductive portions.
16 . The device of claim 11 , wherein the plurality of wirebonds are completely encapsulated by the body of encapsulant material.
17 . The device of claim 11 , wherein the integrated circuit chip comprises at least one of a memory device, a microprocessor and an application specific integrated circuit device.
18 . The device of claim 11 , wherein the plurality of wirebonds are comprised of one or more of gold, aluminum and copper.
19 . The device of claim 11 , wherein the plurality of conductive portions are comprised of aluminum.
20 . The device of claim 11 , wherein the body of encapsulant material comprises an epoxy compound or a molding compound.