Memory device

1. A memory device comprising:

N memory areas divided into a first group and a second group, and selected by N area selection signals, respectively, wherein N is an integer equal to or greater than 4;

N pipe latch groups each having M pipe latches, suitable for storing output data of a corresponding memory area among the N memory areas, wherein M is an integer equal to or greater than 2;

a first pipe output signal generation circuit suitable for generating first pipe output signals of a pipe latch group among the N pipe latch groups corresponding to a memory area included in the first group in response to an area selection signal corresponding to a second reference memory area included the second group; and

a second pipe output signal generation circuit suitable for generating second pipe output signals of the pipe latch group among the N pipe latch groups corresponding to a memory area included in the second group in response to an area selection signal corresponding to a first reference memory area included in the first group.

2. The memory device of claim 1 , further comprising a data output circuit suitable for outputting data of an enabled pipe latch group among the N pipe latch groups corresponding to one among the N memory areas corresponding to an enabled area selection signal among the N area selection signals.

3. The memory device of claim 1 , wherein the first pipe output signal generation circuit sequentially activates the first pipe output signals in response to the area selection signal among the N area selection signals corresponding to the second reference memory area.

4. The memory device of claim 3 , wherein the second pipe output signal generation circuit sequentially activates the second pipe output signals in response to the area selection signal among the N area selection signals corresponding to the first reference memory area.

5. The memory device of claim 3 ,

wherein the first pipe output signal generation circuit comprises M first shift register units electrically coupled to one another in a ring shape,

wherein the M first shift register units perform a shift operation when the area selection signal among the N area selection signals corresponding to the second reference memory area is activated, and

output signals of the M first shift register units are the first pipe output signals.

6. The memory device of claim 5 , wherein each of the M first shift register units includes a D flip-flop.

7. The memory device of claim 4 ,

wherein the second pipe output signal generation circuit comprises M second shift register units electrically coupled to one another in a ring shape,

wherein the M second shift register units perform a shift operation when the area selection signal among the N area selection signals corresponding to the first reference memory area is activated, and

output signals of the M second shift register units are the second pipe output signals.

8. The memory device of claim 7 , wherein each of the M second shift register units includes a D flip-flop.

9. The memory device of claim 7 , wherein the second pipe output signal generation circuit further comprises a blocking unit suitable for preventing shift operations of the M second shift register units before data of the second group is initially outputted when data of the first group is to be outputted prior to the data of the second group.

10. The memory device of claim 1 , wherein each of the N memory areas includes a memory bank.