Phase change memory stack with treated sidewalls
View Patent ↗Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.
1. A memory device comprising:
multiple memory stacks, each memory stack comprising:
a first carbon electrode;
a second carbon electrode in vertically spaced relation to the first carbon electrode;
a chalcogenide-comprising material between the first and second electrodes in the stack;
an adhesion species doped into at least sidewalls of the first and second carbon electrodes; and
a sidewall liner material on sidewalls of the memory stack, wherein the adhesion species is configured to intermix with the carbon of the first and second carbon electrodes and a material of the sidewall liner.
2. The memory device of claim 1 , wherein the memory stack further comprises:
a third carbon electrode in vertically spaced relation to the first and second carbon electrodes and on the opposite side of the second carbon electrode from the first carbon electrode; and
a selector device between the second and third carbon electrodes.
3. The memory device of claim 2 , wherein the selector device comprises one or more of Selenium (Se), Arsenic (As), Germanium (Ge), Tin (Sn), Tellurium (Te), Silicon (Si), Lead (Pb), Carbon (C), and/or Bismuth (Bi).
4. The memory device of claim 1 , wherein the chalcogenide-containing material comprises one or more of Germanium (Ge), Antimony (Sb), Tellurium (Te), and Indium (In).
5. The memory device of claim 4 , wherein the chalcogenide-containing material further comprises one or more of Aluminum (Al), Gallium (Ga), Tin (Sn), Bismuth (Bi), Sulphur (S), Oxygen (O), Gold (Au), Palladium (Pd), Copper (Cu), Cobalt (Co), Silver (Ag), and Platinum (Pt).
6. The memory device of claim 1 , further comprising at least a portion of a tungsten word line, with the first carbon electrode extending over the portion of the tungsten word line.
7. The memory device of claim 1 , wherein the adhesion species is implanted with plasma immersion.
8. The memory device of claim 1 , wherein the sidewall liner material comprises a material that is deposited using a plasma enhanced atomic layer deposition process.
9. The memory device of claim 1 , wherein the adhesion species is boron.
10. The memory device of claim 1 , further comprising a bit line formed adjacent the first carbon electrode, wherein the bit line is a common bit line to multiple memory stacks.
11. The memory device of claim 10 , wherein a first memory stack is formed over a second memory stack and shares the common bit line between the first and second memory stacks.
12. The memory device of claim 1 , wherein the adhesion species is implanted in the sidewall liner.
13. The memory device of claim 1 , wherein the adhesion species is implanted using a BF3 sidewall treatment.
14. A memory system comprising:
a controller; and
a memory device, coupled to the controller, the memory device including multiple memory stacks, each stack comprising:
a first carbon electrode;
a selector device over the first carbon electrode;
a second carbon electrode over the selector device;
a chalcogenide-containing material over the second carbon electrode;
a third carbon electrode over the chalcogenide-containing material; and
an adhesion species doped into sidewalls of at least the second carbon electrode; and
a sidewall liner material on sidewalls of the memory stack wherein the adhesion species is configured to intermix with at least the carbon of the second carbon electrode and a material of the sidewall liner.
15. The memory system of claim 14 , wherein the selector device comprises one or more of Selenium (Se), Arsenic (As), Germanium (Ge), Tin (Sn), Tellurium (Te), Silicon (Si), Lead (Pb), Carbon (C), and/or Bismuth (Bi).
16. The memory system of claim 14 , wherein the chalcogenide-containing material comprises one or more of Germanium (Ge), Antimony (Sb), Tellurium (Te), Indium (In), Aluminum (Al), Gallium (Ga), Tin (Sn), Bismuth (Bi), Sulphur (S), Oxygen (O), Gold (Au), Palladium (Pd), Copper (Cu), Cobalt (Co), Silver (Ag), and/or Platinum (Pt).
17. The memory system of claim 14 , further comprising a dielectric fill material between each of a plurality of memory stacks.