Interfaces and die packages, and appartuses including the same
View Patent ↗A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an IO channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies. The interface device for a memory device includes a control input buffer configured to receive an enable signal through a control pad, a first input buffer configured to receive a first data through a first IO pad in response to a first state of the enable signal, and a second input buffer configured to receive a second data through a second IO pad in response to a second state of the enable signal. The interface device further includes an input multiplexer configured to multiplex the first data and the second data to provide an input data.
1. An apparatus, comprising:
a die package including multiple groups of circuits;
an interface configured to divide a channel between the die package and a controller into multiple channels in response to an external control signal, with at least one channel corresponding to each circuit of the multiple groups of circuits;
wherein the interface device is further configured to divide the channel into multiple input/output (IO) channels; and
wherein one of the multiple JO channels is to be coupled between a first IO pad of the controller and IO pads on each of a first group of the multiple groups of circuits that are disposed in a first portion of the die package, and another one of the multiple IO channels is to be coupled between a second IO pad of the controller and IO pads on each of a second group of the multiple groups of circuits that are disposed in a second portion of the die package.
2. The apparatus of claim 1 , wherein multiple groups of circuits include memory devices.
3. The apparatus of claim 1 , wherein the interface is further configured to select a channel associated with one of the multiple groups of circuits.
4. The apparatus of claim 1 , further comprising an input multiplexer to couple a selected channel to the controller at a time.
5. The apparatus of claim 1 , further comprising an output multiplexer configured to select one channel from the multiple channels, and to divide output data to provide first data and second data in response to the external control signal, the output multiplexer being further configured to provide a first control signal and a second control signal.
6. The apparatus of claim 5 , further comprising:
a first pre-driving circuit configured to provide at least one first buffer signal in response to the first data and the first control signal;
a first output buffer configured to provide a first output data in response to the at least one first buffer signal;
a second pre-driving circuit configured to provide at least one second buffer signal in response to the second data and the second control signal; and
a second output buffer configured to provide a second output data in response to the at least one second buffer signal.
7. The apparatus of claim 5 , wherein the external control signal comprises a selection signal having a first state and a second state.
8. The apparatus of claim 7 , wherein the output multiplexer is configured to provide the first data and the first control signal in response to the first state of the selection signal, and to provide the second data and the second control signal in response to the second state of the selection signal.
9. The apparatus of claim 5 , wherein the output multiplexer is configured to receive a die enable signal as the external control signal, the die enable signal indicating enablement of a memory die in the die package.
10. A memory device, comprising:
multiple groups of circuit devices each containing at least one memory device; and
an interface device to:
receive first data through a first input/output (IO) on the interface device from a first group of the circuit devices,
receive second data through a second IO pad on the interface device from a second group of the circuit devices, and
an input multiplexer configured to multiplex the first data and the second data to provide integrated data in response to an enable signal.
11. The memory device of claim 10 , wherein the input multiplexer is further configured to multiplex the first data and the second data to provide integrated data in response to the enable signal.
12. The memory device of claim 11 , further comprising:
a delay unit configured to delay the integrated data; and
a latch unit configured to store the delayed integrated data.
13. The memory device of claim 10 , wherein the interface device is further configured to divide a channel between the die package and a controller into multiple channels in response to the external control signal, with at least one channel corresponding to each of the multiple groups of circuit devices.
14. The memory device of claim 10 , further comprising an output multiplexer to receive output data from the multiple groups of circuit devices and a selection signal from a memory controller.