IP Library Granted Patent US 10,347,682
Granted Patent B2
US 10,347,682 · App. 15/614,256 · Granted Jul 9, 2019

Shallow trench textured regions and associated methods

Inventors: Homayoon Haddad (Beaverton, OR); Jutao Jiang (Tigard, OR)
Assignee: Sionyx, LLC
H01L27/14643H01L27/1463H01L27/1464H01L27/14625H01L27/14629H01L27/14632H01L27/14689H01L31/028H01L31/02327H01L31/182
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Quick Facts
Patent No.
US 10,347,682
App. No.
15/614,256
Granted
Jul 9, 2019
Kind
B2
Abstract

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.

Claims (59)

1. An optoelectronic device having enhanced absorption of electromagnetic radiation, comprising:

a semiconductor layer having a light incident side and an opposed side, said semiconductor layer having multiple doped regions forming at least one junction,

a textured region comprising a plurality of shallow trench isolation surface features located on the light incident side of the semiconductor layer and configured to interact with incident electromagnetic radiation,

a support substrate coupled to said semiconductor layer, and

a first bonding layer disposed between the semiconductor layer and the support substrate,

wherein said optoelectronic device is a photosensitive imager device capable of detecting visible and infrared electromagnetic radiation.

2. The device of claim 1 , wherein the semiconductor layer is single crystal silicon.

3. The device of claim 1 , wherein the shallow trench isolation surface features are formed in the semiconductor layer.

4. The device of claim 1 , wherein the shallow trench isolation surface features have a substantially uniform height.

5. The device of claim 1 , wherein the shallow trench isolation surface features are not uniform in height.

6. The device of claim 1 , further comprising a device layer coupled to the semiconductor layer on said side opposed to the light incident side.

7. The device of claim 1 , wherein said first bonding layer comprises any of silicon oxide, silicon nitride and amorphous silicon.

8. The device of claim 1 , wherein said semiconductor layer has a thickness in a range of about 1 micron to about 10 microns.

9. The device of claim 1 , wherein said bonding layer has a thickness in a range of about 30 nm to about 3 microns.

10. The device of claim 1 , wherein said bonding layer has a thickness in a range of about 40 nm to about 2 microns.

11. The device of claim 1 , wherein said plurality of shallow trench isolation surface features have a height in a range of about 50 nm to about 20 microns.

12. The device of claim 1 , wherein said shallow trench isolation surface features comprise pyramids.

13. The device of claim 1 , wherein said plurality of shallow trench isolation surface features are formed by using a patterned mask and photolithography followed by etching.

14. The device of claim 1 , wherein said plurality of shallow trench isolation surface features comprise multiple etched levels.

15. The device of claim 1 , wherein said textured region enhances absorption of electromagnetic radiation within said semiconductor layer.

16. The device of claim 1 , wherein said textured region increases optical absorption of the semiconductor layer over an electromagnetic spectrum range of at least about 700 nm to about 1100 nm.

17. The device of claim 1 , wherein said textured region increases effective optical path length of light as it passes through the semiconductor layer.

18. The device of claim 1 , wherein said textured region allows the semiconductor layer to experience multiple passes of light.

19. The device of claim 1 , further comprising a second bonding layer positioned between the first bonding layer and the support substrate.

20. The device of claim 19 , further comprising a reflector layer disposed between the first bonding layer and the second bonding layer.

21. The device of claim 1 , wherein the shallow trench isolation surface features are arranged according to a pattern.

22. The device of claim 21 , wherein the pattern is an at least substantially uniform grid.

23. The device of claim 21 , wherein the pattern is a non-uniform arrangement.

24. A method of making an optoelectronic device, comprising:

bonding a semiconductor layer to a support substrate, wherein bonding the semiconductor layer to the support substrate includes:

depositing a first bonding layer onto the semiconductor layer; and

bonding the first bonding layer to a second bonding layer disposed on the support substrate; and

creating a plurality of shallow trench isolation surface features on a light incident side of said semiconductor layer.

25. The method of claim 24 , wherein the step of creating the plurality of shallow trench isolation surface features comprises generating an array of surface features using shallow trench isolation etching.

26. The device of claim 1 , further comprising deep trench isolation for isolating the device.

27. The device of claim 26 , wherein said deep trench isolation provides light trapping functionality.

28. An optoelectronic device having enhanced absorption of electromagnetic radiation, comprising:

a semiconductor layer having a light incident side and an opposed side, said semiconductor layer having multiple doped regions forming at least one junction,

a textured region comprising a plurality of shallow trench isolation surface features located on the light incident side of the semiconductor layer and configured to interact with incident electromagnetic radiation,

a support substrate coupled to said semiconductor layer, and

a first bonding layer disposed between the semiconductor layer and the support substrate,

a second bonding layer positioned between the first bonding layer and the support substrate, and

a reflector layer disposed between the first bonding layer and the second bonding layer.

29. The device of claim 28 , wherein said shallow trench isolation surface features comprise pyramids.

30. The device of claim 28 , wherein said plurality of shallow trench isolation surface features are formed by using a patterned mask and photolithography followed by etching.

31. The device of claim 28 , wherein said semiconductor layer has a thickness in a range of about 1 micron to about 10 microns.

32. The device of claim 28 , wherein the shallow trench isolation surface features have a substantially uniform height.

33. The device of claim 28 , wherein the shallow trench isolation surface features are not uniform in height.

34. The device of claim 28 , wherein said plurality of shallow trench isolation surface features have a height in a range of about 50 nm to about 20 microns.

35. The device of claim 28 , wherein said photosensitive imager device is capable of detecting visible and infrared electromagnetic radiation.

36. The device of claim 28 , wherein said textured region enhances absorption of electromagnetic radiation within said semiconductor layer.

37. The device of claim 28 , wherein said textured region increases optical absorption of the semiconductor layer over an electromagnetic spectrum range of at least about 700 nm to about 1100 nm.

38. The device of claim 28 , wherein said textured region increases effective optical path length of light as it passes through the semiconductor layer.

39. The device of claim 28 , wherein said textured region allows the semiconductor layer to experience multiple passes of light.

40. The device of claim 28 , further comprising deep trench isolation for isolating the device.

41. The device of claim 40 , wherein said deep trench isolation provides light trapping functionality.

42. The device of claim 28 , wherein the shallow trench isolation surface features are arranged according to a pattern.

43. The device of claim 42 , wherein the pattern is an at least substantially uniform grid.

44. The device of claim 42 , wherein the pattern is a non-uniform arrangement.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE TYPOGRAPHICAL ERROR IN THE NEWLY MERGED ENTITY NAME TO SIONYX, LLC. PREVIOUSLY RECORDED ON REEL 042980 FRAME 0805. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded May 24, 2019
From: SIONYX, INC.
To: SIONYX, LLC
Reel/Frame 049302/0863 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2017
From: HADDAD, HOMAYOON; JIANG, JUTAO
To: SIONYX, INC.
Reel/Frame 042796/0440 →
MERGER AND CHANGE OF NAME Recorded Jun 23, 2017
From: SIONYX, INC.; SIONY, LLC
To: SIONY, LLC
Reel/Frame 042980/0805 →
Continuity (4)
Continuation 14884181 · Oct 15, 2015
Continuation 14084392 · Nov 19, 2013
Provisional Application 61841326 · Jun 29, 2013
Related Publication 20170271394A1 · Sep 21, 2017