Structure and method for providing line end extensions for fin-type active regions
A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
1. A method, comprising:
forming an isolation feature in a semiconductor substrate;
forming a first fin-like active region in the semiconductor substrate and contacting the isolation feature;
forming a dummy gate stack on an end region of the isolation feature, wherein the dummy gate stack extends above the first fin-like active region;
forming a recess in the first fin-like active region, wherein the recess is formed between the end region and a first region of the first fin-like active region; and
forming a functional gate stack on the first region of the first fin-like active region.
2. The method of claim 1 , further comprising: growing an epitaxial material in the recess.
3. The method of claim 1 , wherein the forming the dummy gate stack includes forming a dummy gate stack having a different dimension that the functional gate stack.
4. The method of claim 1 , further comprising:
forming a second fin-like active region wherein the dummy gate stack extends above the second fin-like active region.
5. The method of claim 4 , wherein the first fin-like active region and the second fin-like active region are collinear.
6. The method of claim 4 , wherein the first fin-like active region and the second fin-like active region are adjacent fins having a portion of the isolation feature disposed therebetween, and wherein the first fin-like active region and the second fin-like active region are on a same side of the dummy gate stack.
7. The method of claim 1 , further comprising:
etching a recess in the first fin-like active region using a spacer element disposed on the dummy gate stack as a masking element during the etching the recess.
8. A method of fabricating a semiconductor structure, comprising:
providing a substrate having a plurality of isolation features formed in a semiconductor substrate;
etching back the plurality of isolation features to provide a first fin-type active region formed in the semiconductor substrate, wherein the first fin-type active region extends in a first direction and a second fin-type active region formed on the semiconductor substrate, wherein the second fin-type active region is parallel to the first fin-type active region and a next adjacent active region to the first fin-type active region in a second direction;
forming a gate stack disposed over an isolation feature of the plurality of isolation features and on an end region of the first fin-type active region and an end region of the second fin-type active region, wherein the gate stack extends in the second direction, the second direction perpendicular to the first direction; and
etching a first recess in the first fin-type active region and a second recess in the second fin-type active region, wherein the first recess and second recess are adjacent and spaced a distance from the isolation feature.
9. The method of claim 8 , further comprising:
forming an epitaxial material in the etched first and second recesses.
10. The method of claim 9 , wherein the epitaxial material extrudes above a surface of the first fin-type active region.
11. The method of claim 8 , wherein the etching the first recess forms the first recess offset from the isolation feature.
12. The method of claim 11 , further comprising:
forming an epitaxial material in the first recess, wherein the epitaxial material is grown only on semiconductor surfaces.
13. The method of claim 8 , wherein the forming the gate stack includes forming a silicon oxide layer and a polysilicon layer; and further comprising forming another gate stack, wherein the another gate stack is a functional gate stack including high-k dielectric material and a metal layer.
14. The method of claim 8 , further comprising:
wherein the gate stack is disposed on the isolation feature having a recessed top surface from a top surface of the first fin-type active region, thereby providing a bottom surface of the gate stack below a top surface of the first fin-type active region.
15. The method of claim 14 , by performing a chemical mechanical polish (CMP) a top surface of the gate stack is coplanar with a top surface of a functional gate stack disposed over the first fin-type active region.
16. A method of fabricating a semiconductor device, comprising: providing a first plurality of fin-like active regions formed in a silicon substrate and oriented in a first direction, wherein each of the first plurality of fin-like active regions are parallel and spaced a first distance in a second direction from one another, the second direction being perpendicular the first direction, the first plurality of fin-like active regions including a first fin-like active region and a second fin-like active region;
forming a shallow trench isolation (STI) feature in the silicon substrate and adjacent an end region of each of the first plurality of fin-like active regions, wherein an uppermost surface of the STI feature is below an uppermost surface of each of the first plurality of fin-like active regions;
depositing a dummy gate on the uppermost surface of the STI feature and the uppermost surface of each of the first plurality of fin-like active regions, wherein the dummy gate extends in a second direction to overlap with the end region of each of the first plurality of fin-like active regions and wherein at least one portion of the dummy gate is physically touching the uppermost surface of the STI feature and the uppermost top surface of at least one of the plurality of first fin-like active regions;
etching a first recess in the first fin-like active region and a second recess in the second fin-like active region; and
growing an epitaxial material in the first and second recesses.
17. The method of claim 16 , further comprising:
forming an active gate over the first fin-like active region and the second fin-like active region.
18. The method of claim 17 , wherein the active gate extends over a third fin-like active region.
19. The method of claim 16 , wherein the at least one portion of the dummy gate includes a spacer element, and the spacer element is physically touching the uppermost surface of the STI feature and the uppermost top surface of each of the plurality of first fin-like active regions.