Stacked semiconductor device structure and method

1. A stacked semiconductor device structure comprising:

a first semiconductor device comprising a first major surface and a second major surface opposite to the first major surface, the second major surface comprising a recessed region bounded by sidewall portions, the sidewall portions having outer surfaces defining peripheral edge segments of the first semiconductor device;

a first conductive layer disposed adjoining at least portions of the recessed region; and

a second semiconductor device comprising a third major surface and a fourth major surface opposite to the third major surface,

wherein:

a first portion of the second semiconductor device is electrically coupled to the first conductive layer within the recessed region, and

at least a portion of the second semiconductor device is disposed within the recessed region.

2. The structure of claim 1 , wherein:

the first semiconductor device comprises a first singulated region of semiconductor material having the first major surface and the second major surface; and

the second semiconductor device comprises a second singulated region of semiconductor material having the third major surface and the fourth major surface.

3. The structure of claim 1 further comprising:

a conductive lead frame comprising a plurality of conductive lead structures; and

a package body encapsulating at least portions of the conductive lead frame, the first semiconductor device, and the second semiconductor device, wherein:

the sidewall portions are electrically coupled to a first conductive lead structure and a second conductive lead structure respectively;

the fourth major surface is electrically coupled to a third conductive lead structure;

a portion of the first semiconductor device is electrically coupled to a fourth conductive lead structure; and

portions of the first conductive lead structure, the second conductive lead structure, the third conductive lead structure, and the fourth conductive lead structure are exposed to an outside of the package body.

4. The structure of claim 3 , wherein:

another portion of the first semiconductor device is electrically coupled to a fifth conductive lead structure; and

a second portion of the second semiconductor device is electrically coupled to a sixth conductive lead structure.

5. The structure of claim 4 , wherein:

a third portion of the second semiconductor device is electrically coupled to a seventh conductive lead structure; and

portions of the fifth conductive lead structure, the sixth conductive lead structure, and the seventh conductive lead structure are exposed to the outside of the package body.

6. The structure of claim 4 , wherein the second portion of the second semiconductor device is electrically coupled to the sixth conductive lead structure using a through-semiconductor via.

7. The structure of claim 3 further comprising a third semiconductor device electrically coupled to one or more of a first control electrode of the first semiconductor device and a second control electrode of the second semiconductor device.

8. The structure of claim 7 , wherein:

the portion of the first semiconductor device is electrically coupled to the fourth conductive lead structure with a conductive clip; and

the third semiconductor device is attached to the conductive clip.

9. The structure of claim 1 , wherein the first conductive layer is disposed along one or more of an inner surface of the sidewall portions and tip portions of the sidewall portions.

10. The structure of claim 1 , wherein:

the first semiconductor device and the second semiconductor device comprise MOSFETs;

the second semiconductor device is bounded on a first pair of opposing sides by the sidewall portions; and

a second pair of opposing sides of the second semiconductor device extend laterally away from edges of the first semiconductor device.

11. A stacked semiconductor device comprising:

a first semiconductor device comprising:

a first major surface and a second major surface opposite to the first major surface, the second major surface comprising a recessed surface portion bounded by a first sidewall portion extending outward from the recessed surface portion in cross-sectional view to define a recessed region;

a first active device region disposed adjacent to the first major surface; and

a first conductive layer disposed adjoining at least the recessed surface portion; and

a second semiconductor device comprising:

a third major surface and a fourth major surface opposite to the third major surface, and

a second active device region disposed adjacent to the third major surface, wherein:

a first portion of the second semiconductor device is electrically coupled to the first conductive layer within the recessed region.

12. The stacked semiconductor device of claim 11 further comprising:

a conductive substrate having a plurality of conductive lead structures, wherein:

the first semiconductor device comprises a second sidewall portion disposed opposite to the first sidewall portion; and

the first sidewall portion is electrically coupled to a first conductive lead structure and the second sidewall portion is electrically coupled to a second conductive lead structure;

the fourth major surface is electrically coupled to a third conductive lead structure;

a portion of the first semiconductor device is electrically coupled to a fourth conductive lead structure; and

a package body encapsulating at least portions of the conductive substrate, the first semiconductor device, and the second semiconductor device.

13. The stacked semiconductor device of claim 12 , wherein:

another portion of the first semiconductor device is electrically coupled to a fifth conductive lead structure;

a second portion of the second semiconductor device is electrically coupled to a sixth conductive lead structure;

a third portion of the second semiconductor device is electrically coupled to a seventh conductive lead structure; and

portions of the first conductive lead structure, the second conductive lead structure, the third conductive lead structure, the fourth conductive lead structure, the fifth conductive lead structure, the sixth conductive lead structure, and the seventh conductive lead structure are exposed to an outside of the package body.

14. The stacked semiconductor device of claim 13 , wherein the second portion of the second semiconductor device is electrically coupled with a through-substrate via.

15. The stacked semiconductor device of claim 12 further comprising a third semiconductor device electrically coupled to one or more of a first control electrode of the first semiconductor device and a second control electrode of the second semiconductor device.

16. A stacked semiconductor device comprising:

a first semiconductor device comprising:

a first major surface and a second major surface opposite to the first major surface, the second major surface comprising a recessed surface portion bounded by a first sidewall portion extending outward from the recessed surface portion in cross-sectional view to define a recessed region;

a first active device region disposed adjacent to the first major surface; and

a first conductive layer disposed adjoining at least the recessed surface portion; and

a second semiconductor device comprising:

a third major surface and a fourth major surface opposite to the third major surface, and

a second active device region disposed adjacent to the third major surface, wherein:

a first portion of the second semiconductor device is electrically coupled to the first conductive layer within the recessed region, and

the first sidewall portion extends to overlap at least part of a side surface of the second semiconductor device.

17. The stacked semiconductor device of claim 16 further comprising:

a conductive substrate having a plurality of conductive lead structures, wherein:

the first semiconductor device comprises a second sidewall portion disposed opposite to the first sidewall portion; and

the first sidewall portion is electrically coupled to a first conductive lead structure and the second sidewall portion is electrically coupled to a second conductive lead structure;

the fourth major surface is electrically coupled to a third conductive lead structure;

a portion of the first semiconductor device is electrically coupled to a fourth conductive lead structure; and

a package body encapsulating at least portions of the conductive substrate, the first semiconductor device, and the second semiconductor device.

18. The stacked semiconductor device of claim 17 , wherein:

another portion of the first semiconductor device is electrically coupled to a fifth conductive lead structure;

a second portion of the second semiconductor device is electrically coupled to a sixth conductive lead structure;

a third portion of the second semiconductor device is electrically coupled to a seventh conductive lead structure; and

portions of the first conductive lead structure, the second conductive lead structure, the third conductive lead structure, the fourth conductive lead structure, the fifth conductive lead structure, the sixth conductive lead structure, and the seventh conductive lead structure are exposed to an outside of the package body.

19. The stacked semiconductor device of claim 18 , wherein the second portion of the second semiconductor device is electrically coupled with a through-substrate via.

20. The stacked semiconductor device of claim 17 further comprising a third semiconductor device electrically coupled to one or more of a first control electrode of the first semiconductor device and a second control electrode of the second semiconductor device.