IP Library Granted Patent US 10,269,669
Granted Patent B2
US 10,269,669 · App. 15/616,908 · Granted Apr 23, 2019

Semiconductor package and method of forming the same

Inventors: Ying-Shin Han (Hsinchu, TW); Yen-Miao Lin (Miaoli County, TW); Chung-Chih Chen (Hsinchu, TW); Hsien-Liang Meng (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L23/10H01L21/4817H01L23/053H01L23/145H01L23/36H01L23/3675H01L23/42H01L24/13H01L24/16H01L24/32H01L24/73H01L24/81H01L24/92H01L2224/13111H01L2224/13116H01L2224/13139H01L2224/13147H01L2224/13155H01L2224/16145H01L2224/16227H01L2224/32145H01L2224/32225H01L2224/32245H01L2224/73204H01L2224/73253H01L2224/81815H01L2224/92125H01L2224/92225H01L2924/163H01L2924/16251H01L2924/3511H01L2924/3512H01L2924/35121
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Quick Facts
Patent No.
US 10,269,669
App. No.
15/616,908
Granted
Apr 23, 2019
Kind
B2
Abstract

A semiconductor package includes a substrate, an integrated circuit die, a lid and an adhesive. The integrated circuit die is disposed over the substrate. The lid is disposed over the substrate. The lid includes a cap portion and a foot portion extending from a bottom surface of the cap portion. The cap portion and the foot portion define a recess, and the integrated circuit die is accommodated in the recess. The adhesive includes a sidewall portion and a bottom portion. The sidewall portion contacts a sidewall of the foot portion. The bottom portion extends from the sidewall portion to between a bottom surface of the foot portion and the substrate.

Claims (33)

1. A semiconductor package, comprising:

a substrate;

an integrated circuit die over the substrate;

a lid over the substrate, wherein the lid comprises a cap portion and a foot portion extending from a bottom surface of the cap portion, wherein the cap portion and the foot portion define a recess, and the integrated circuit die is accommodated in the recess;

an adhesive comprising a sidewall portion and a bottom portion, wherein the sidewall portion contacts an inner sidewall of the foot portion, wherein the bottom portion extends from the sidewall portion to between a bottom surface of the foot portion and the substrate, and wherein the adhesive covers a majority of the inner sidewall of the foot portion; and

an underfill between the substrate and the integrated circuit die, wherein the sidewall portion of the adhesive is spaced apart from the underfill.

2. The semiconductor package of claim 1 , wherein the adhesive is substantially conformal to a corner between the bottom surface and the inner sidewall of the foot portion.

3. The semiconductor package of claim 1 , wherein the inner sidewall and the bottom surface of the foot portion form a first corner, the sidewall portion and the bottom portion of the adhesive form a second corner, and wherein the first corner overlaps with the second corner.

4. The semiconductor package of claim 1 , wherein the sidewall portion and the bottom portion are made of a homogeneous adhesive material.

5. The semiconductor package of claim 1 , wherein the sidewall portion of the adhesive is enclosed by the foot portion of the lid.

6. The semiconductor package of claim 1 , wherein the integrated circuit die is enclosed by the sidewall portion of the adhesive.

7. The semiconductor package of claim 1 , wherein the sidewall portion of the adhesive is between the foot portion of the lid and the integrated circuit die.

8. The semiconductor package of claim 7 , wherein the sidewall portion of the adhesive is spaced apart from the integrated circuit die.

9. The semiconductor package of claim 1 , wherein the bottom portion forms a relatively thick ring, and wherein the sidewall portion forms a relatively thin ring stacked over the relatively thick ring.

10. The semiconductor package of claim 9 , wherein the relatively thick ring and the relatively thin ring are concentrically stacked.

11. A semiconductor package, comprising:

a substrate;

an integrated circuit die over the substrate;

a lid over the substrate, the lid having a bottom surface and a recess in the bottom surface, wherein the integrated circuit die is received in the recess; and

an adhesive comprising a base and a protrusion, wherein the base extends into a gap between the substrate and the bottom surface of the lid, wherein the protrusion protrudes from the base into the recess along a sidewall of the recess, and wherein the adhesive has a bottom surface non-parallel with a bottom surface of the lid.

12. The semiconductor package of claim 11 , wherein the protrusion covers a majority of the sidewall of the recess of the lid.

13. The semiconductor package of claim 11 , wherein the base and the protrusion coincide at a corner between the bottom surface of the lid and the sidewall of the recess.

14. The semiconductor package of claim 11 , wherein the protrusion forms an adhesive ring, and wherein the sidewall of the recess forms a non-adhesive ring around the adhesive ring.

15. The semiconductor package of claim 11 , wherein the base and the protrusion are monolithically connected.

16. A semiconductor package, comprising:

a substrate;

a lid over the substrate and comprising a cap portion and a foot portion extending from the cap portion towards the substrate;

an integrated circuit die between the cap portion of the lid and the substrate; and

an adhesive on the substrate, wherein the foot portion of the lid is embedded in the adhesive, wherein the adhesive comprises a first portion on an inner sidewall of the foot portion and a second portion on an outer sidewall of the foot portion, and a top end of the first portion is in a position higher than a top end of the second portion.

17. The semiconductor package of claim 16 , wherein the first portion of the adhesive is separated from the integrated circuit die.

18. The semiconductor package of claim 1 , wherein the bottom portion of the adhesive is in contact with a curved surface of the substrate.

19. The semiconductor package of claim 11 , wherein a top of the adhesive is in a position lower than top of the integrated circuit die.

20. The semiconductor package of claim 1 , further comprising a thermal interface material between the integrated circuit die and the lid.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2017
From: HAN, YING-SHIN; LIN, YEN-MIAO; CHEN, CHUNG-CHIH; MENG, HSIEN-LIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 042656/0116 →
Continuity (2)
Provisional Application 62434411 · Dec 14, 2016
Related Publication 20180166351A1 · Jun 14, 2018