Semiconductor device and method

1. A method comprising:

forming a gate stack over a substrate;

growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si;

growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities;

depositing a metal layer over the semiconductor cap layer;

annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities, the annealing comprising performing a plurality of annealing processes, each successive one of the annealing processes being performed at a higher temperature than a previous one of the annealing processes, wherein substantially all of the Ge impurities in the semiconductor cap layer are segregated to the silicide layer after a final annealing process of the annealing processes; and

forming a metal contact electrically coupled to the silicide layer.

2. The method of claim 1 , wherein annealing the metal layer and the semiconductor cap layer consumes all of the semiconductor cap layer.

3. The method of claim 1 , wherein annealing the metal layer and the semiconductor cap layer does not consume all of the semiconductor cap layer.

4. The method of claim 1 , wherein the source/drain region is doped with P.

5. The method of claim 1 , wherein the semiconductor cap layer is doped with P.

6. The method of claim 1 , wherein the silicide layer has a concentration of the Ge impurities of from 1% to 20%.

7. The method of claim 6 , wherein a largest concentration of the Ge impurities in the silicide layer is at a depth of from 1 nm to 10 nm from a top surface of the silicide layer.

8. The method of claim 1 , further comprising:

forming an inter-layer dielectric (ILD) over the source/drain region; and

forming an opening in the ILD, the opening exposing a top surface of the source/drain region, wherein the growing the source/drain region and the growing the semiconductor cap layer are performed in different growing steps.

9. A method comprising:

forming a gate stack over a substrate;

growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si;

forming an inter-layer dielectric (ILD) over the source/drain region;

forming an opening in the ILD, the opening exposing the source/drain region;

growing a semiconductor cap layer in the opening and on the source/drain region, the semiconductor cap layer being SiGe or SiGeP;

depositing a metal layer in the opening and on a top surface of the semiconductor cap layer;

annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, wherein annealing the metal layer and the semiconductor cap layer consumes all of the semiconductor cap layer; and

forming a metal contact electrically coupled to the silicide layer.

10. The method of claim 9 , wherein the silicide layer has a concentration of Ge of from 1% to 20%.

11. The method of claim 10 , wherein a largest concentration of the Ge in the silicide layer is at a depth of from 1 nm to 10 nm.

12. The method of claim 9 , wherein the annealing the metal layer and the semiconductor cap layer comprises performing a plurality of annealing processes, each successive annealing process of the plurality of annealing processes is performed at a higher temperature.

13. The method of claim 12 , wherein the silicide layer is TiSi 2 , and Ge in the semiconductor cap layer segregates at grain boundaries of the TiSi 2 during a final annealing process of the plurality of annealing processes.

14. A method comprising:

forming a gate stack over a substrate;

growing, in a first growing step, a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si;

forming an inter-layer dielectric (ILD) over the source/drain region;

forming an opening in the ILD, the opening exposing a top surface of the source/drain region;

growing, in a second growing step, a semiconductor cap layer on portions of the source/drain region exposed by the opening, the semiconductor cap layer being Si doped with Ge impurities, the second growing step being different from the first growing step;

depositing a metal layer in the opening and on the top surface of the semiconductor cap layer;

annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the annealing being performed until substantially all of the Ge impurities in the semiconductor cap layer are segregated to the silicide layer; and

forming a metal contact electrically coupled to the silicide layer.

15. The method of claim 14 , wherein the silicide layer has a concentration of Ge of from 1% to 20%.

16. The method of claim 14 , wherein the annealing the metal layer and the semiconductor cap layer comprises performing a plurality of annealing processes, each successive annealing process of the plurality of annealing processes is performed at a higher temperature.

17. The method of claim 16 , wherein the silicide layer is TiSi 2 , and Ge in the semiconductor cap layer segregates at grain boundaries of the TiSi 2 during a final annealing process of the plurality of annealing processes.

18. The method of claim 15 , wherein a largest concentration of the Ge impurities in the silicide layer is located at a point disposed a first depth from a top surface of the silicide layer.

19. The method of claim 18 , wherein the first depth is from 1 nm to 10 nm.

20. The method of claim 14 , wherein a thicknesses of the semiconductor cap layer is less than a thicknesses of the source/drain region before the annealing.