IP Library Granted Patent US 10,153,210
Granted Patent B1
US 10,153,210 · App. 15/618,131 · Granted Dec 11, 2018

Semiconductor device and method for fabricating the same

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Quick Facts
Patent No.
US 10,153,210
App. No.
15/618,131
Granted
Dec 11, 2018
Kind
B1
Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a shallow trench isolation (STI) around the first fin-shaped structure; forming a first oxide layer on the first fin-shaped structure; and then forming a second oxide layer on the first oxide layer and the STI.

Claims (27)

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a first region and a second region;

forming a first fin-shaped structure on the first region;

forming a shallow trench isolation (STI) around the first fin-shaped structure;

after forming the STI performing an in-situ steam generation (ISSG) process to form a first oxide layer on the first fin-shaped structure so that the first oxide layer covers a top surface and sidewalls of the first fin-shaped structure without extending to a top surface of the STI; and

forming a second oxide layer on and directly contacting the first oxide layer and the STI.

2. The method of claim 1 , further comprising:

forming a second fin-shaped structure on the second region;

forming the STI around the second fin-shaped structure;

forming the first oxide layer on the first fin-shaped structure and the second fin-shaped structure; and

forming the second oxide layer on the first oxide layer on the second region.

3. The method of claim 2 , further comprising:

forming a patterned mask on the first region;

removing the second oxide layer and the first oxide layer on the second region; and

forming a third oxide layer on the second fin-shaped structure.

4. The method of claim 1 , further comprising performing an atomic layer deposition (ALD) process to form the second oxide layer.

5. The method of claim 1 , wherein a thickness of the first oxide layer is less than a thickness of the second oxide layer.

6. The method of claim 1 , further comprising:

forming a first liner on the first fin-shaped structure;

forming a second liner on the first liner; and

forming a dielectric layer on the second liner.

7. The method of claim 6 , wherein the first liner and the second liner comprise same material.

8. The method of claim 6 , wherein the first liner and the second liner comprise silicon oxide.

9. The method of claim 6 , further comprising performing an in-situ steam generation (ISSG) process to form the first liner.

10. The method of claim 6 , further comprising performing an atomic layer deposition (ALD) process to form the second liner.

11. The method of claim 6 , wherein the thicknesses of the first liner and the second liner are equivalent.

12. The method of claim 6 , wherein a thickness of the first liner is greater than a thickness of the first oxide layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2017
From: LIN, CHUN-HAO; CHEN, HSIN-YU; LU, CHUN-TSEN; HSIEH, SHOU-WEI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 042656/0474 →