Memory with symmetric read current profile and read method thereof
Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes a first decoder coupled to the first memory array, a second decoder coupled to the second memory array, and an output buffer. The first decoder obtains first data from the first memory array according a first address signal. The second decoder obtains second data from the second memory array according the first address signal. The output buffer selectively provides the first data or the second data as an output according to a control signal. The first data is complementary to the second data.
1. A memory, comprising:
a first memory array formed by a plurality of memory cells; a second memory array formed by a plurality of memory cells; and a read circuit, comprising:
a first decoder coupled to the first memory array configured to obtain first data from the first memory array according a first address signal;
a second decoder coupled to the second memory array configured to simultaneously obtain second data from the second memory array according the first address signal; and
an output buffer configured to selectively provide the first data or the second data as an output according to a control signal,
wherein each binary value of the first data from the first memory array is complementary to each binary value of the second data from the second memory array.
2. The memory as claimed in claim 1 , wherein the read circuit further comprises:
a first sense amplifier coupled between the first decoder and the output buffer, and configured to provide a first sensing signal according to a reference signal and the first data; and
a second sense amplifier coupled between the second decoder and the output buffer, and configured to provide a second sensing signal according to the reference signal and the second data.
3. The memory as claimed in claim 2 , wherein the output buffer comprises:
a first selector coupled to the first sense amplifier and the second sense amplifier, and configured to selectively provide the first sensing signal or the second sensing signal as the output according to the control signal.
4. The memory as claimed in claim 2 , wherein the first decoder comprises:
a second selector coupled between the first memory array and the first sense amplifier, and configured to selectively provide a signal of the first data to the first sense amplifier according to the first address signal,
wherein the second decoder comprises:
a third selector coupled between the second memory array and the second sense amplifier, and configured to selectively provide a signal of the second data to the second sense amplifier according to the first address signal,
wherein the signal of the first data is complementary to the signal of the second data.
5. The memory as claimed in claim 1 , further comprising:
a writing circuit configured to store first programming data to the first memory array according to a second address signal and to store second programming data to the second memory array according to the second address signal,
wherein the first programming data is complementary to the second programming data.
6. The memory as claimed in claim 1 , wherein the read circuit further comprises:
an exchange unit configured to selectively provide one of a first sensing signal corresponding to the first data and a second sensing signal corresponding to the second data as a first signal and selectively provide the other as a second signal according to the control signal,
wherein the output buffer is coupled to the exchange unit and configured to selectively provide the first signal or the second signal as the output according to the control signal.
7. The memory as claimed in claim 1 , wherein when the first memory array is a main array and the second memory array is an auxiliary array, the control signal controls the output buffer to provide the first data as the output, and when the first memory array is an auxiliary array and the second memory array is a main array, the control signal controls the output buffer to provide the second data as the output.
8. A memory, comprising:
a first memory array formed by a plurality of memory cells;
a second memory array formed by a plurality of memory cells; and
a read circuit, comprising:
a first sense amplifier configured to provide a first sensing signal according to a reference signal and first data;
a second sense amplifier configured to simultaneously provide a second sensing signal according to the reference signal and second data;
an exchange unit configured to selectively couple the first sense amplifier to one of the first memory array and the second memory array so as to provide the first data according to a control signal, and to selectively couple the second sense amplifier to the other memory array according to the control signal so as to provide the second data;
a random number generator configured to generate the control signal; and an output buffer configured to selectively provide the first sensing signal or the second sensing signal as an output according to the control signal,
wherein the first data from the first memory array is complementary to the second data from the second memory array.
9. The memory as claimed in claim 8 , wherein the read circuit further comprises:
a first decoder coupled between the first memory array and the exchange unit configured to provide the first data from the first memory array according a first address signal; and
a second decoder coupled between the second memory array and the exchange unit configured to provide the second data from the second memory array according the first address signal.
10. The memory as claimed in claim 9 , wherein the first decoder comprises:
a first selector coupled between the first memory array and the exchange unit, and configured to selectively provide a signal of the first data stored in the first memory array to the exchange unit according to the first address signal,
wherein the second decoder comprises:
a second selector coupled between the second memory array and the exchange unit, and configured to selectively provide a signal of the second data stored in the second memory array to the exchange unit according to the first address signal,
wherein the signal of the data stored in the first memory array is complementary to the signal of the data stored in the second memory array,
wherein the exchange unit selectively provides the signal of the data stored in one of the first and second memory array as the first data according to the control signal, and provides the signal of the data stored in the other memory array as the second data according to the control signal.
11. The memory as claimed in claim 8 , wherein the exchange unit comprises:
a third selector coupled between the first memory array, the second memory array and the first sense amplifier, and configured to selectively provide data stored in one of the first memory array and the second memory array as the first data according to the control signal; and
a fourth selector coupled between the first memory array, the second memory array and the second sense amplifier, and configured to selectively provide the data stored in the other memory array as the second data according to the control signal.
12. The memory as claimed in claim 8 , further comprising:
a writing circuit configured to store first programming data to the first memory array according to a second address signal and to store second programming data to the second memory array according to the second address signal,
wherein the first programming data is complementary to the second programming data.
13. The memory as claimed in claim 8 , wherein the number of memory cells in the first memory array is identical to the number of memory cells in the second memory array.
14. The memory as claimed in claim 8 , wherein the control signal controls the exchange unit to couple the second memory array to the first sense amplifier and couple the first memory array to the second sense amplifier, wherein when the first memory array is a main array and the second memory array is an auxiliary array, the control signal controls the output buffer to provide the second sensing signal as the output, and when the first memory array is an auxiliary array and the second memory array is a main array, the control signal controls the output buffer to provide the first sensing signal as the output.
15. A read method for a memory, comprising:
obtaining first data from a first memory array of the memory according to an address signal;
simultaneously obtaining second data from a second memory array of the memory according the address signal; and
selectively providing the first data or the second data as an output according to a control signal,
wherein each binary value of the first data from the first memory array is complementary to each binary value of the second data from the second memory array.
16. The method as claimed in claim 15 , further comprising:
selectively providing one of a first sensing signal corresponding to the first data and a second sensing signal corresponding to the second data as a first signal and selectively provide the other as a second signal according to the control signal,
wherein the first signal or the second signal is provided as the output according to the control signal.
17. The method as claimed in claim 15 , wherein when the first memory array is a main array and the second memory array is an auxiliary array, the first data is provided as the output according to the control signal, and when the first memory array is an auxiliary array and the second memory array is a main array, the second data is provided as the output according to the control signal.
18. The method as claimed in claim 15 , wherein a read circuit of the memory comprises:
a first decoder coupled to the first memory array and configured to obtain the first data from the first memory array according the address signal;
a second decoder coupled to the second memory array and configured to obtain the second data from the second memory array according the address signal; and
an output buffer configured to selectively provide the first data or the second data as the output according to the control signal.
19. The method as claimed in claim 18 , wherein the read circuit of the memory further comprising:
a first sense amplifier coupled between the first decoder and the output buffer, and configured to provide a first sensing signal according to a reference signal and the first data; and
a second sense amplifier coupled between the second decoder and the output buffer, and configured to provide a second sensing signal according to the reference signal and the second data.
20. The method as claimed in claim 19 , wherein the output buffer comprises:
a first selector coupled to the first sense amplifier and the second sense amplifier, and configured to selectively provide the first sensing signal or the second sensing signal as the output according to the control signal.