Biased transistor module

1. A biased-transistor-module comprising:

a module-input-terminal;

a module-output-terminal;

a reference-terminal;

a module-supply-terminal configured to receive a supply voltage;

a module-reference-voltage-terminal configured to receive a module reference voltage;

a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and

a bias-circuit comprising:

a first-bias-transistor having a first-bias-control-terminal, a first-bias-first-conduction-channel-terminal and a first-bias-second-conduction-channel-terminal;

a first-bias-resistor;

a second-bias-transistor having a second-bias-control-terminal, a second-bias-first-conduction-channel-terminal and a second-bias-second-conduction-channel-terminal; and

a second-bias-resistor;

wherein:

the first-bias-first-conduction-channel-terminal is connected to the input-signal-node;

the first-bias-second-conduction-channel-terminal is connected to the reference-terminal;

the first-bias-resistor is connected between the first-bias-first-conduction-channel-terminal and the first-bias-control-terminal;

the second-bias-second-conduction-channel-terminal is connected to the input-signal-node;

the second-bias-first-conduction-channel-terminal is connected to the module-supply-terminal; and

the second-bias-resistor is connected between the second-bias-control-terminal and the module-reference-voltage-terminal; and

further comprising a first-additional-capacitor connected between the second-bias-control-terminal and the second-bias-second-conduction-channel-terminal.

2. The biased-transistor-module of claim 1 , further comprising a second-additional-capacitor connected between the first-bias-control-terminal and the first-bias-second-conduction-channel-terminal.

3. The biased-transistor-module of claim 1 , further comprising:

a first-reference-transistor having a first-reference-control-terminal, a first-reference-first-conduction-channel-terminal and a first-reference-second-conduction-channel-terminal;

a second-reference-transistor having a second-reference-control-terminal, a second-reference-first-conduction-channel-terminal and a second-reference-second-conduction-channel-terminal; and

a reference-current-terminal,

wherein:

the first-reference-first-conduction-channel-terminal is connected to an intermediate-reference-node;

the first-reference-second-conduction-channel-terminal is connected to the reference-terminal;

the first-reference-control-terminal is connected to the intermediate-reference-node;

the second-reference-second-conduction-channel-terminal is connected to the intermediate-reference-node;

the second-reference-first-conduction-channel-terminal is connected to the module-reference-voltage-terminal;

the second-reference-control-terminal is connected to the module-reference-voltage-terminal; and

the module-reference-voltage-terminal is connected to the reference-current-terminal.

4. The biased-transistor-module of claim 3 ,

further comprising a reference-capacitor connected between the module-reference-voltage-terminal and the first-reference-second-conduction-channel-terminal.

5. The biased-transistor-module of claim 3 ,

further comprising a first-reference-resistor connected between the first-reference-control-terminal and the intermediate-reference-node.

6. The biased-transistor-module of claim 3 ,

further comprising a second-reference-resistor connected between the second-reference-control-terminal and the module-reference-voltage-terminal.

7. The biased-transistor-module of claim 3 ,

further comprising a voltage-offset-terminal connected to the first-bias-control-terminal, wherein the voltage-offset-terminal is configured to provide an offset voltage to the biased-transistor-module.

8. The biased-transistor-module of claim 7 ,

further comprising a first-offset-resistor connected between the voltage-offset-terminal and the first-bias-control-terminal.

9. The biased-transistor-module of claim 7 ,

further comprising a second-offset-resistor connected between the voltage-offset-terminal and the first-reference-control-terminal.

10. The biased-transistor-module of claim 1 , wherein

the main-transistor comprises a main-area, the first-bias-transistor comprises a first-area and the second-bias-transistor comprises a second-area, and:

the ratio of the main-area to the first-area is greater than 2; or

the ratio of the main-area to the second-area is greater than 2.

11. The biased-transistor-module of claim 1 ,

further comprising an input-capacitor connected in series between the input-signal-node and the module-input-terminal.

12. The biased-transistor-module of claim 1

wherein the first-bias-transistor is configured to provide current to cancel an avalanche current generated by the main-transistor.

13. A system comprising:

a plurality of the biased-transistor-modules of claim 1 ;

a system-supply-terminal;

a system-reference-terminal;

a system-input-terminal; and

a system-output-terminal,

wherein:

each module-supply-terminal, of each of the plurality of biased-transistor-modules, is connected to the system-supply-terminal;

each reference-terminal, of each of the plurality of biased-transistor-modules, is connected to the system-reference-terminal;

each of the plurality of the biased-transistor-modules is connected in cascade or parallel between the system-input-terminal and the system-output-terminal.

14. A Class-C amplifier, or a Doherty amplifier, comprising the biased-transistor-module of claim 1 .

15. A biased-transistor-module comprising:

a module-input-terminal;

a module-output-terminal;

a reference-terminal;

a module-supply-terminal configured to receive a supply voltage;

a module-reference-voltage-terminal configured to receive a module reference voltage;

a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and

a bias-circuit comprising:

a first-bias-transistor having a first-bias-control-terminal, a first-bias-first-conduction-channel-terminal and a first-bias-second-conduction-channel-terminal;

a first-bias-resistor;

a second-bias-transistor having a second-bias-control-terminal, a second-bias-first-conduction-channel-terminal and a second-bias-second-conduction-channel-terminal; and

a second-bias-resistor;

wherein:

the first-bias-first-conduction-channel-terminal is connected to the input-signal-node;

the first-bias-second-conduction-channel-terminal is connected to the reference-terminal;

the first-bias-resistor is connected between the first-bias-first-conduction-channel-terminal and the first-bias-control-terminal;

the second-bias-second-conduction-channel-terminal is connected to the input-signal-node;

the second-bias-first-conduction-channel-terminal is connected to the module-supply-terminal; and

the second-bias-resistor is connected between the second-bias-control-terminal and the module-reference-voltage-terminal; and

further comprising a first-additional-capacitor connected between the first-bias-control-terminal and the first-bias-second-conduction-channel-terminal.

16. A biased-transistor-module comprising:

a module-input-terminal;

a module-output-terminal;

a reference-terminal;

a module-supply-terminal configured to receive a supply voltage;

a module-reference-voltage-terminal configured to receive a module reference voltage;

a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and

a bias-circuit comprising:

a first-bias-transistor having a first-bias-control-terminal, a first-bias-first-conduction-channel-terminal and a first-bias-second-conduction-channel-terminal;

a first-bias-resistor;

a second-bias-transistor having a second-bias-control-terminal, a second-bias-first-conduction-channel-terminal and a second-bias-second-conduction-channel-terminal; and

a second-bias-resistor;

wherein:

the first-bias-first-conduction-channel-terminal is connected to the input-signal-node;

the first-bias-second-conduction-channel-terminal is connected to the reference-terminal;

the first-bias-resistor is connected between the first-bias-first-conduction-channel-terminal and the first-bias-control-terminal;

the second-bias-second-conduction-channel-terminal is connected to the input-signal-node;

the second-bias-first-conduction-channel-terminal is connected to the module-supply-terminal; and

the second-bias-resistor is connected between the second-bias-control-terminal and the module-reference-voltage-terminal; and

further comprising:

a first-reference-transistor having a first-reference-control-terminal, a first-reference-first-conduction-channel-terminal and a first-reference-second-conduction-channel-terminal;

a second-reference-transistor having a second-reference-control-terminal, a second-reference-first-conduction-channel-terminal and a second-reference-second-conduction-channel-terminal; and

a reference-current-terminal,

wherein:

the first-reference-first-conduction-channel-terminal is connected to an intermediate-reference-node;

the first-reference-second-conduction-channel-terminal is connected to the reference-terminal;

the first-reference-control-terminal is connected to the intermediate-reference-node;

the second-reference-second-conduction-channel-terminal is connected to the intermediate-reference-node;

the second-reference-first-conduction-channel-terminal is connected to the module-reference-voltage-terminal;

the second-reference-control-terminal is connected to the module-reference-voltage-terminal; and

the module-reference-voltage-terminal is connected to the reference-current-terminal.