Application store model for dynamic reconfiguration of a field-programmable gate array (FPGA)

1. A computing device comprising:

a field-programmable gate array (FPGA) and a reconfigurable FPGA image associated with the FPGA;

user interface logic to cause at least one upgradable capability of the FPGA to be displayed to a user of the computing device and receive a selection of a selected upgradable capability of the at least one upgradable capability and an acceptance of a license for the selected upgradable capability from the user;

license management logic to issue a license to enable the selected upgradable capability of the FPGA in exchange for the acceptance of the license by the user; and

FPGA image update logic to obtain an update to the reconfigurable FPGA image associated with the FPGA in response to issuance of the license and to cause the update to the reconfigurable FPGA image to be installed on the FPGA to enable the selected upgradable capability of the FPGA.

2. The computing device of claim 1 , wherein

to obtain the update to the reconfigurable FPGA image comprises to obtain FPGA runtime language (RTL) logic associated with the selected upgradable capability;

the FPGA image update logic is further to request a bitstream for the update to the reconfigurable FPGA image to be synthesized from the FPGA runtime language (RTL) logic; and

to cause the update to the reconfigurable FPGA image to be installed on the FPGA comprises to cause the bitstream to be installed on the FPGA.

3. The computing device of claim 1 , wherein

the user interface logic is further to:

cause the at least one upgradable capability of the FPGA to be displayed to the user in association with a user selection of an application associated with the at least one upgradable capability.

4. The computing device of claim 1 , wherein

the FPGA image update logic is further to:

verify the update to the reconfigurable FPGA image prior to causing the update to the reconfigurable FPGA image to be installed on the FPGA;

cause the update to the reconfigurable FPGA image to be installed after verifying the update; and

notify an operating system of the computing device of the update to the reconfigurable FPGA image, wherein the operating system is further to expose the selected upgradable capability of the FPGA to at least one component of a software stack managed by the operating system.

5. The computing device of claim 4 , wherein

the update to the reconfigurable FPGA image is to be installed at a first runtime without rebooting the computing device,

the operating system is to be notified of the update to the reconfigurable FPGA image at the first runtime without rebooting the computing device, and

the selected upgradable capability of the FPGA is exposed to the at least one component of the software stack at the first runtime without rebooting the computing device.

6. The computing device of claim 4 , wherein

the operating system exposes the selected upgradable capability of the FPGA by configuring an operating system driver or library that is used for dynamic linking to an application, and

the application dynamically acquires new functionality or achieves improved performance subsequent to enablement of the selected upgradable capability of the FPGA.

7. The computing device of claim 1 , further comprising:

virtual machine monitor logic to execute a virtual machine monitor, wherein

the virtual machine monitor manages a first guest virtual machine and a second guest virtual machine,

the virtual machine monitor is to expose the selected upgradable capability of the FPGA to one of the first guest virtual machine and the second guest virtual machine, and

the exposed guest virtual machine is enabled to use the selected upgradable capability of the FPGA at a first runtime.

8. The computing device of claim 1 , further comprising:

trusted execution environment logic to establish a trusted execution environment; and

verification logic to verify the FPGA image update logic and the reconfigurable FPGA image for the FPGA during a secure boot of the computing device within the trusted execution environment.

9. The computing device of claim 8 , wherein

to verify the FPGA image update logic is to calculate a first measurement of the FPGA image update logic and to compare the first measurement to a first whitelisted measurement for the FPGA image update logic and to verify the FPGA image update logic if the first measurement matches the first whitelisted measurement; and

to verify the reconfigurable FPGA image is to calculate a second measurement of the reconfigurable FPGA image and to compare the second measurement to a second whitelisted measurement of the reconfigurable FPGA image and to verify the reconfigurable FPGA image if the second measurement matches the second whitelisted measurement.

10. The computing device of claim 1 , wherein the FPGA image update logic is to notify system software of the computing device that the selected upgradable capability of the FPGA has been enabled.

11. The computing device of claim 1 , wherein

the FPGA image update logic is further to update an inventory of FPGA capabilities of the computing device to indicate that the selected upgradable FPGA capability is currently valid.

12. The computing device of claim 1 , further comprising:

FPGA configuration manager logic to manage configuration of the FPGA, wherein

the license authorizes enabling the selected upgradable FPGA capability until occurrence of a license expiration event associated with the license; and

the license management logic and the FPGA configuration manager logic cause the selected upgradable FPGA capability to be disabled upon the occurrence of the license expiration event.

13. The computing device of claim 12 , wherein

the FPGA configuration manager logic is further to record a transaction for the issuance of the license and enablement of the selected upgradable FPGA capability.

14. At least one non-transitory computer-readable medium comprising a plurality of executable computer instructions stored thereon that, in response to being executed by a processor, cause a computing device to:

cause at least one upgradable capability of an FPGA of the computing device to be displayed to a user of the computing device and receive a selection of a selected upgradable capability of the at least one upgradable capability and an acceptance of a license for the selected upgradable capability from the user, wherein the FPGA is associated with a reconfigurable FPGA image;

issue a license to enable the selected upgradable capability of the FPGA in exchange for the acceptance of the license by the user;

obtain an update to the reconfigurable FPGA image associated with the FPGA in response to issuance of the license; and

cause the update to the reconfigurable FPGA image to be installed on the FPGA to enable the selected upgradable capability of the FPGA.

15. The at least one computer-readable medium of claim 14 , wherein

to obtain the update to the reconfigurable FPGA image comprises to obtain FPGA runtime language (RTL) logic associated with the selected upgradable capability; and

the instructions further cause the computing device to:

request a bitstream for the update to the reconfigurable FPGA image to be synthesized from the FPGA runtime language (RTL) logic, wherein to cause the update to the reconfigurable FPGA image to be installed on the FPGA comprises to cause the bitstream to be installed on the FPGA.

16. The at least one computer-readable medium of claim 14 , wherein the instructions further cause the computing device to:

cause the at least one upgradable capability of the FPGA to be displayed to the user in association with a user selection of an application associated with the at least one upgradable capability.

17. The at least one computer-readable medium of claim 14 , wherein the instructions further cause the computing device to:

verify the update to the reconfigurable FPGA image prior to causing the update to the reconfigurable FPGA image to be installed on the FPGA;

cause the update to the reconfigurable FPGA image to be installed after verifying the update; and

notify an operating system of the computing device of the update to the reconfigurable FPGA image, wherein the operating system is further to expose the selected upgradable capability of the FPGA to at least one component of a software stack managed by the operating system.

18. The at least one computer-readable medium of claim 17 , wherein

the operating system exposes the selected upgradable capability of the FPGA by configuring an operating system driver or library that is used for dynamic linking to an application, and

the application dynamically acquires new functionality or achieves improved performance subsequent to enablement of the selected upgradable capability of the FPGA.

19. The at least one computer-readable medium of claim 14 , wherein the instructions further cause the computing device to:

execute a virtual machine monitor, wherein

the virtual machine monitor is to manage a first guest virtual machine and a second guest virtual machine,

the virtual machine monitor is to expose the selected upgradable capability of the FPGA to one of the first guest virtual machine and the second guest virtual machine, and

the exposed guest virtual machine is enabled to use the selected upgradable capability of the FPGA at a first runtime.

20. The at least one computer-readable medium of claim 14 , wherein the instructions further cause the computing device to:

establish a trusted execution environment, and

execute verification logic within the trusted execution environment; wherein

the verification logic is further to verify the reconfigurable FPGA image during a secure boot of the computing device, and

the verification logic is further to verify, during the secure boot, an FPGA image update logic that is to install the update to the reconfigurable FPGA image on the FPGA.

21. The at least one computer-readable medium of claim 20 , wherein

to verify the FPGA image update logic is to calculate a first measurement of the FPGA image update logic and to compare the first measurement to a first whitelisted measurement for the FPGA image update logic and to verify the FPGA image update logic if the first measurement matches the first whitelisted measurement; and

to verify the reconfigurable FPGA image is to calculate a second measurement of the reconfigurable FPGA image and to compare the second measurement to a second whitelisted measurement of the reconfigurable FPGA image and to verify the reconfigurable FPGA image if the second measurement matches the second whitelisted measurement.

22. The at least one computer-readable medium of claim 14 , wherein the instructions are further to:

notify system software of the computing device that the selected upgradable capability of the FPGA has been enabled.

23. The at least one computer-readable medium of claim 14 , wherein the instructions are further to:

update an inventory of FPGA capabilities of the computing device to indicate that the selected upgradable FPGA capability is currently valid.

24. The at least one computer-readable medium of claim 14 , wherein

the license authorizes enabling the selected upgradable FPGA capability until occurrence of a license expiration event associated with the license; and

the instructions are further to cause the selected upgradable FPGA capability to be disabled upon the occurrence of the license expiration event.

25. The at least one computer-readable medium of claim 14 , wherein the instructions are further to:

record a transaction for the issuance of the license and enablement of the selected upgradable FPGA capability.

26. A computer-implemented method comprising:

causing at least one upgradable capability of an FPGA of a computing device to be displayed to a user of the computing device and receiving a selection of a selected upgradable capability of the at least one upgradable capability and an acceptance of a license for the selected upgradable capability from the user, wherein the FPGA is associated with a reconfigurable FPGA image;

issuing a license to enable the selected upgradable capability of the FPGA in exchange for the acceptance of the license by the user;

obtaining an update to the reconfigurable FPGA image associated with the FPGA in response to issuance of the license; and

causing the update to the reconfigurable FPGA image to be installed on the FPGA to enable the selected upgradable capability of the FPGA.

27. The method of claim 26 , wherein

obtaining the update to the reconfigurable FPGA image comprises obtaining FPGA runtime language (RTL) logic associated with the selected upgradable capability; and

the method further comprises:

requesting a bitstream for the update to the reconfigurable FPGA image to be synthesized from the FPGA runtime language (RTL) logic, wherein causing the update to the reconfigurable FPGA image to be installed on the FPGA comprises causing the bitstream to be installed on the FPGA.

28. The method of claim 26 , further comprising:

causing the at least one upgradable capability of the FPGA to be displayed to the user in association with a user selection of an application associated with the at least one upgradable capability.

29. The method of claim 26 , further comprising:

verifying the update to the reconfigurable FPGA image prior to causing the update to the reconfigurable FPGA image to be installed on the FPGA;

causing the update to the reconfigurable FPGA image to be installed after verifying the update; and

notifying an operating system of the computing device of the update to the reconfigurable FPGA image, wherein the operating system is further to expose the selected upgradable capability of the FPGA to at least one component of a software stack managed by the operating system.

30. The method of claim 26 , wherein

the operating system exposes the selected upgradable capability of the FPGA by configuring an operating system driver or library that is used for dynamic linking to an application, and

the application dynamically acquires new functionality or achieves improved performance subsequent to enablement of the selected upgradable capability of the FPGA.

31. The method of claim 26 , further comprising:

executing a virtual machine monitor, wherein

the virtual machine monitor is to manage a first guest virtual machine and a second guest virtual machine,

the virtual machine monitor is to expose the selected upgradable capability of the FPGA to one of the first guest virtual machine and the second guest virtual machine, and

the exposed guest virtual machine is enabled to use the selected upgradable capability of the FPGA at a first runtime.

32. The method of claim 26 , wherein

the license authorizes enabling the selected upgradable FPGA capability until occurrence of a license expiration event associated with the license; and

the method further comprising causing the selected upgradable FPGA capability to be disabled upon the occurrence of the license expiration event.

33. An apparatus comprising:

means for causing at least one upgradable capability of an FPGA of a computing device to be displayed to a user of the computing device and to receive a selection of a selected upgradable capability of the at least one upgradable capability and an acceptance of a license for the selected upgradable capability from the user, wherein the FPGA is associated with a reconfigurable FPGA image;

means for issuing a license to enable the selected upgradable capability of the FPGA in exchange for the acceptance of the license by the user;

means for obtaining an update to the reconfigurable FPGA image associated with the FPGA in response to issuance of the license; and

means for causing the update to the reconfigurable FPGA image to be installed on the FPGA to enable the selected upgradable capability of the FPGA.

34. The apparatus of claim 33 , wherein

the means for obtaining the update to the reconfigurable FPGA image comprises means for obtaining FPGA runtime language (RTL) logic associated with the selected upgradable capability; and

wherein the apparatus further comprises:

means for requesting a bitstream for the update to the reconfigurable FPGA image to be synthesized from the FPGA runtime language (RTL) logic, wherein the means for causing the update to the reconfigurable FPGA image to be installed on the FPGA comprise means for causing the bitstream to be installed on the FPGA.

35. The apparatus of claim 33 , wherein

the license authorizes enabling the selected upgradable FPGA capability until occurrence of a license expiration event associated with the license; and

the apparatus further comprises means for causing the selected upgradable FPGA capability to be disabled upon the occurrence of the license expiration event.