IP Library Granted Patent US 10,134,597
Granted Patent B2
US 10,134,597 · App. 15/620,458 · Granted Nov 20, 2018

Apparatuses including memory cells with gaps comprising low dielectric constant materials

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Quick Facts
Patent No.
US 10,134,597
App. No.
15/620,458
Granted
Nov 20, 2018
Kind
B2
Abstract

Various embodiments include apparatuses and electronic devices. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is located between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first gap and a second gap. In various embodiments, the gaps are air gaps. Additional apparatuses and methods are disclosed.

Claims (29)

1. An electronic device, comprising:

a pair of dielectric materials located substantially parallel to one another; and

a charge storage material disposed substantially between the pair of dielectric materials and having a first surface and an opposing second surface, the first surface and the second surface being substantially parallel to and separated from each of the pair of dielectric materials by a first gap and a second gap, respectively, that are in contact with the first surface and the opposing second surface, respectively, of the charge storage material, each gap being filled with a low-dielectric-constant material.

2. The electronic device of claim 1 , wherein the low-dielectric-constant material comprises air.

3. The electronic device of claim 1 , wherein the low-dielectric-constant material comprises a gas.

4. The electronic device of claim 1 , wherein the first dielectric material and the second dielectric material are comprised of the same material.

5. The electronic device of claim 1 , wherein the first dielectric material and the second dielectric material are comprised of different materials.

6. The electronic device of claim 1 , further comprising a third dielectric material between the conductive material and the charge storage material.

7. The electronic device of claim 6 , wherein the third dielectric material comprises silicon dioxide and silicon nitride.

8. An apparatus comprising:

a first dielectric material;

a second dielectric material;

a conductive material located between the first dielectric material and the second dielectric material; and

a charge storage element located substantially between the first dielectric material and the second dielectric material and further being located adjacent to the conductive material, the charge storage element having a first surface and a second surface, the first surface and the second surface being substantially separated electrically from the first dielectric material and the second dielectric material, respectively, by a first gap and a second gap that are in contact with the first surface and the second surface, respectively, of the charge storage element.

9. The apparatus of claim 8 , wherein the charge storage element comprises a substantially toroidal-shaped floating gate that is substantially circular.

10. The apparatus of claim 8 , wherein the apparatus includes a memory device comprising the first dielectric material, the second dielectric material, the conductive material, and the charge storage element.

11. The apparatus of claim 10 , wherein the apparatus further comprises a controller coupled to the memory device.

12. The apparatus of claim 8 , further comprising a tunnel dielectric separating the first gap and the second gap from a semiconductor material.

13. The apparatus of claim 12 , wherein a ratio of a thickness of the conductive material to a thickness of the tunnel dielectric may be from about 10 to 1 to about 4 to 1.

14. An apparatus comprising:

a pair of dielectric materials located substantially parallel to one another;

a conductive material located between the pair of dielectric materials; and

a charge storage element configured to store charge to represent a data state, the charge storage element located substantially between the pair of dielectric materials and adjacent to the conductive material, the charge storage element having a first surface and a second surface, the first surface being substantially separated from a first dielectric material by a low dielectric constant material, and the second surface being substantially separated electrically from a second dielectric material by the low dielectric constant material, the low dielectric constant material comprising a gap, the low dielectric constant material substantially contacting the first surface and the second surface, respectively, of the charge storage element.

15. The apparatus of claim 14 , wherein the conductive material substantially surrounds an outer periphery of the charge storage element.

16. The apparatus of claim 14 , wherein the charge storage element comprises a toroidal-shaped floating gate.

17. The apparatus of claim 16 , wherein a cross-section of the toroidal-shaped floating gate is substantially rectangular.

18. The apparatus of claim 16 , wherein a cross-section of the toroidal-shaped floating gate is substantially square.

19. The apparatus of claim 16 , wherein the gap is configured to reduce a parasitic capacitance between the toroidal-shaped floating gate and a control gate to a level lower than a parasitic capacitance of a gap formed from a high-k dielectric.

20. The apparatus of claim 14 , further comprising a dielectric material between an outer periphery of the charge storage element and an inner periphery of the conductive material.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →