Package process and package structure

1. A package structure, comprising:

a circuit substrate;

a first semiconductor device disposed on the circuit substrate;

a first insulation layer covering a sidewall of the first semiconductor device;

a second insulation layer covering the first insulation layer;

a third insulation layer disposed on the first insulation layer, in contact with the second insulation layer, and covering sidewalls of the second insulation layer;

a second semiconductor device disposed on the circuit substrate and electrically connected to the first semiconductor device, wherein the second semiconductor device is flip-chip bonded to the first semiconductor device; and

a fourth insulation layer covering the second semiconductor device, wherein a portion of the fourth insulation layer fills up a space between the first semiconductor device and the circuit substrate,

wherein a maximum length of the second insulation layer is not larger than a maximum length of the second semiconductor device.

2. The package structure of claim 1 , wherein the first semiconductor device includes a plurality of via structures.

3. The package structure of claim 2 , wherein the plurality of via structures are silicon-via structures.

4. The package structure of claim 1 , wherein the third insulation layer covers the first semiconductor device.

5. The package structure of claim 1 , further comprising a conductive element in the second insulation layer.

6. The package structure of claim 1 , wherein a top surface of the first semiconductor device is aligned with a top surface of the first insulation layer.

7. The package structure of claim 1 , wherein the second insulation layer is in contact with a top surface of the first semiconductor device.

8. The package structure of claim 1 , wherein a maximum length of the first semiconductor device is smaller than the maximum length of the second semiconductor device.

9. The package structure of claim 8 , wherein

the maximum length of the second insulation layer corresponds to a length of the second insulation layer in a cross-sectional view of the package structure that is greatest out of all other lengths of the second insulation layer in the cross-sectional view;

the maximum length of the second semiconductor device corresponds to a length of the second semiconductor device in the cross-sectional view of the package structure that is greatest out of all other lengths of the second semiconductor device in the cross-sectional view; and

the maximum length of the first semiconductor device corresponds to a length of the first semiconductor device in the cross-sectional view of the package structure that is greatest out of all other lengths of the first semiconductor device in the cross-sectional view.

10. The package structure of claim 8 , wherein

the second semiconductor device is flip-chip bonded to the first semiconductor device along a surface of the second semiconductor device; and

the maximum length of the second insulation layer, the maximum length of the first semiconductor device, and the maximum length of the second semiconductor device are parallel to the surface of the second semiconductor device.

11. The package structure of claim 1 , wherein the second semiconductor device covers the first semiconductor device.

12. The package structure of claim 1 , wherein the second semiconductor device covers the first insulation layer and the second insulation layer.

13. The package structure of claim 1 , wherein the fourth insulation layer is in contact with the third insulation layer.

14. The package structure of claim 1 , wherein the fourth insulation layer covers the circuit substrate.

15. The package structure of claim 1 , further comprising a plurality of conductive elements between the second semiconductor device and the first semiconductor device.

16. The package structure of claim 1 , wherein a thickness of the first semiconductor device is smaller than or equal to 4 mil.

17. The package structure of claim 1 , wherein the second insulation layer further covers a top surface of the first semiconductor device.

18. The package structure of claim 1 , wherein a top surface of the first semiconductor device is exposed from the first insulation layer.

19. The package structure of claim 1 , wherein the maximum length of the second insulation layer is equal to the maximum length of the second semiconductor device.

20. The package structure of claim 1 , wherein a side wall of the first insulation layer is coplanar with a sidewall of the third insulation layer.