Semiconductor memory device and operating method thereof

1. A semiconductor memory device, comprising: a memory cell array including a plurality of memory blocks; a voltage generator that applies a pre-erase voltage and an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation; a read and write circuit that applies an initial setting voltage to bit lines of at least one memory block during the erase operation; and a control logic that controls the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the pre-erase voltage and the erase voltage to the source line, wherein the initial setting voltage is greater than OV.

2. The semiconductor memory device of claim 1 , wherein the initial setting voltage is lower than a power voltage.

3. The semiconductor memory device of claim 1 , wherein the voltage generator applies the erase voltage by increasing the pre-erase voltage to the erase voltage.

4. The semiconductor memory device of claim 1 , wherein the read and write circuit further controls the bit lines to be in a floating state when applying the erase voltage to the source line after applying the initial setting voltage to the bit lines.

5. The semiconductor memory device of claim 1 , wherein the voltage generator further controls word lines of the at least one memory block to be in a floating state when applying the erase voltage.

6. The semiconductor memory device of claim 5 , wherein the voltage generator further applies a positive set voltage to the word lines before controlling the word lines to be in the floating state.

7. The semiconductor memory device of claim 1 , wherein the voltage generator further applies a positive set voltage to a gate of a pipe transistor included in the at least one memory block before applying the erase voltage to the source line, and further controls the pipe transistor to be in a floating state when applying the erase voltage to the source line.

8. The semiconductor memory device of claim 1 , wherein the voltage generator further sequentially applies a predetermined positive voltage and a ground voltage to the source line before applying the erase voltage to the source line.

9. A method for operating a semiconductor device, the method comprising:

applying an initial setting voltage to bit lines of a selected memory block among a plurality of memory blocks, wherein the initial setting voltage is greater than 0V;

floating the bit lines after applying the initial setting voltage to the bit lines; and

applying a pre-erase voltage and an erase voltage to a source line of the selected memory block when the bit lines are floated.

10. The method of claim 9 , wherein the initial setting voltage is lower than a power voltage.

11. The method of claim 9 , wherein the applying of the pre-erase voltage and the erase voltage comprises:

applying the pre-erase voltage to the source line for a predetermined time when the bit lines are floated; and

increasing the pre-erase voltage to the erase voltage.

12. The method of claim 11 ,

wherein the applying of the initial setting voltage to the bit lines further comprises applying a positive set voltage to word lines of the selected memory block, and

wherein the increasing of the pre-erase voltage further comprises floating the word lines.

13. The method of claim 11 , wherein the increasing of the pre-erase voltage further comprises floating a source selection line of the selected memory block.

14. The method of claim 11 , further comprising sequentially applying a predetermined positive voltage and a ground voltage to the source line before applying the pre-erase voltage to the source line.