Virtual switch for multi-compartment mixed critical network communications

1. A multi-core processing system comprising:

a first input/output interface configured to transmit data over a first network based on a first network protocol;

a second input/output interface configured to transmit data over a second network based on a second network protocol;

a plurality of processing cores;

one or more hardware accelerators coupled to the first and second input/output interfaces; and

one or more memory devices storing software enabling virtual processing resources of the plurality of processing cores and virtual memory to be assigned to support:

a first compartment implementing one or more first virtual machines;

a second compartment implementing one or more second virtual machines; and

a programmable virtual switch configured to provide an interface between the first and second virtual machines and the first and second input/output interfaces, wherein:

the programmable virtual switch comprises:

a shared memory permitting communications between the first and second virtual machines;

a first compartment switch providing an interface between the one or more first virtual machines and the first input/output interface and/or the one or more hardware accelerators; and

a second compartment switch providing an interface between the one or more second virtual machines and the second input/output interface and/or the one or more hardware accelerators, wherein the first and second compartment switches are configured to communicate via the shared memory; and

the programmable virtual switch is further configured to dynamically allocate the one or more hardware accelerators for use by the first or second virtual machines, wherein:

the first compartment switch is configured to access the shared memory only during the first compartment execution; and

the second compartment switch is configured to access the shared memory only during the second compartment execution.

2. The multi-core processing system of claim 1 , wherein the shared memory comprises a common area for the first and second virtual machines to read and write data packets.

3. The multi-core processing system of claim 1 , wherein the shared memory comprises a plurality of sub-regions, a different sub-region being associated with each of the first and second virtual machines, wherein the programmable virtual switch is configured to deny read/write access to at least one of said sub-regions by at least one of said first and second virtual machines.

4. The multi-core processing system of claim 1 , wherein the programmable virtual switch further comprises a security manager configured to perform packet authentication of data packets transmitted and/or received by the first and/or second virtual machines.

5. The multi-core processing system of claim 1 , wherein the virtual switch is adapted to write a special authorization code to one or more registers associated with the one or more processing cores, the special authorization code indicating that the packet transmission is initiated by the virtual switch, wherein a monitor layer is configured to authorize the packet transmission based on the special authorization code.

6. The multi-core processing system of claim 1 , wherein the first network is one or more of:

an Ethernet network

an AVB (audio video bridging) network;

an MOST (media oriented systems transport) network, and the second network is one or more of:

a CAN (controlled area network); and

a CAN-FD (controlled area network with flexible data rate).

7. A method of communication comprising:

providing a virtual processing system comprising a plurality of processing cores, and one or more memory devices storing software enabling virtual processing resources of the plurality of processing cores and virtual memory to be assigned to support a first compartment implementing one or more first virtual machines, a second compartment implementing one or more second virtual machines, and a programmable virtual switch;

routing, by the programmable virtual switch, first data from one of the first and second virtual machines to one or more of:

another of the first and second virtual machines;

a first input/output interface configured to transmit data over a first network based on a first network protocol; and

a second input/output interface configured to transmit data over a second network based on a second network protocol, wherein the first data is routed to the first or second input/output interface via one or more hardware accelerators, the method further comprising dynamically allocating, by the programmable virtual switch, the one or more hardware accelerators for transmitting data over the first or second network, wherein:

the programmable virtual switch comprises:

a shared memory permitting communications between the first and second virtual machines;

a first compartment switch providing an interface between the one or more first virtual machines and the first input/output interface and/or the one or more hardware accelerators; and

a second compartment switch providing an interface between the one or more second virtual machines and the second input/output interface and/or the one or more hardware accelerators;

the first and second compartment switches are configured to communicate via the shared memory;

the first compartment switch is configured to access the shared memory only during first compartment execution; and

the second compartment switch is configured to access the shared memory only during second compartment execution.

8. The method of claim 7 , wherein the first data is routed from one of the first virtual machines to one of the second virtual machines via:

the first compartment switch accessible by the one or more first virtual machines;

the second compartment switch accessible by the one or more second virtual machines; and

the shared memory accessible by the first and second compartment switches.

9. A non-transitory computer readable medium storing computing instructions adapted to implement, when executed by a processing device, the method of claim 7 .