IP Library Granted Patent US 10,103,094
Granted Patent B2
US 10,103,094 · App. 15/626,687 · Granted Oct 16, 2018

Method and structures for heat dissipating interposers

Inventors: Cyprian Emeka Uzoh (San Jose, CA); Pezhman Monadgemi (Fremont, CA); Terrence Caskey (Santa Cruz, CA); Fatima Lina Ayatollahi (Fremont, CA); Belgacem Haba (Saratoga, CA); Charles G. Woychik (San Jose, CA); Michael Newman (Fort Collins, CO)
Assignee: Invensas Corporation
H01L23/49827H01L21/76829H01L23/36H01L23/367H01L23/3736H01L23/481H01L23/49838H01L23/49866H01L21/76898H01L23/3677H01L2924/00H01L2924/0002
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Quick Facts
Patent No.
US 10,103,094
App. No.
15/626,687
Granted
Oct 16, 2018
Kind
B2
Abstract

An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.

Claims (28)

1. A microelectronic assembly comprising,

an interconnect element, comprising:

a semiconductor or insulating material layer having first and second ends and a first thickness extending between the first and second ends, the first end of the semiconductor or insulating material layer defining a first surface of the interconnect element;

a thermally conductive layer having a second thickness of at least 10 microns and defining a second surface of the interconnect element;

a plurality of conductive elements extending from the first surface of the interconnect element to the second surface of the interconnect element, wherein each of the plurality of conductive elements further includes an edge surface extending between a first conductive end and a second conductive end of the respective conductive element; and

a dielectric layer between at least a portion of each conductive element and the thermally conductive layer and between at least a portion of each conductive element and the semiconductor or insulating material layer; and

a barrier layer extending adjacent at least a portion of the dielectric layer and extending between the semiconductor or insulating material layer and the thermally conductive layer; and

a microelectronic element attached to the interconnect element and including contact elements at a surface thereof, wherein the contact elements are electrically connected with the plurality of conductive elements,

wherein the thermally conductive layer extends along the respective edge surfaces of the conductive elements, such that end surfaces of the plurality of conductive elements are exposed at a surface of the thermally conductive layer.

2. The assembly of claim 1 , wherein the contact elements are electrically connected with the conductive elements by joints between the contact elements and the first and second end surfaces of the conductive elements.

3. The assembly of claim 1 , wherein the interconnect element is a first interconnect element, the assembly further comprising a second interconnect element electrically connected to the microelectronic element through the first interconnect element.

4. The assembly of claim 3 , wherein the second interconnect element is positioned at a same surface of the first interconnect element to which the microelectronic element is attached.

5. The assembly of claim 4 , wherein the second interconnect element is posited at a surface of the first interconnect element opposite the same surface to which the microelectronic element is attached.

6. The assembly of claim 4 , wherein the first and second interconnect element are connected to one another via a redistribution layer disposed at the same surface of the first interconnect element.

7. The assembly of claim 4 , further comprising a third interconnect element positioned at a surface of the first interconnect element opposite the same surface, the third interconnect element electrically connected with the microelectronic element and the first and second interconnect element.

8. The assembly of claim 5 , wherein the microelectronic element is further connected to the second interconnect element through vias in the first interconnect element.

9. The assembly of claim 1 , wherein the barrier layer extends between the dielectric layer and the semiconductor or insulating material layer.

10. The assembly of claim 1 , wherein the barrier layer extends between the dielectric layer and the thermally conductive layer.

11. The assembly of claim 1 , wherein the dielectric layer extends along the first end surface of the semiconductor material.

12. The assembly of claim 1 , wherein the barrier layer electrically insulates the semiconductor or insulating material layer from the thermally conductive layer.

13. The assembly of claim 1 , wherein the barrier layer prevents contamination of semiconductor material layer with particles from the thermally conductive layer.

14. The assembly of claim 1 , wherein the barrier prevents contamination of semiconductor material layer with particles from the thermally conductive layer and electrically insulates the semiconductor or insulating material layer from the thermally conductive layer.

15. The assembly of claim 1 , wherein the barrier layer further extends along the second end surface of the semiconductor or insulating material layer.

16. The assembly of claim 1 , wherein the semiconductor or insulating material layer overlies the thermally conductive layer.

17. The assembly of claim 1 , wherein the thermally conductive layer overlies the semiconductor or insulating material layer.

18. The assembly of claim 1 , wherein the thermally conductive layer is electrically connected with at least one of the conductive elements such that the conductive element is configured as a ground element.

19. The assembly of claim 1 , wherein the thermally conductive layer includes copper and wherein the thermally conductive layer has a thickness of between 10 and 300 microns.

20. The assembly of claim 1 , wherein the thermally conductive layer includes a highly thermally conductive material of one of graphite and carbon, and wherein the thermally conductive layer has a thickness of between 10 and 200 microns.

Assignments (4)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0661 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073689/0793 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2017
From: UZOH, CYPRIAN EMEKA; MONADGEMI, PEZHMAN; CASKEY, TERRENCE; AYATOLLAHI, FATIMA LINA; HABA, BELGACEM; WOYCHIK, CHARLES G.; NEWMAN, MICHAEL
To: INVENSAS CORPORATION
Reel/Frame 043489/0251 →
Continuity (3)
Division 14815282 · Jul 31, 2015
Division 13720346 · Dec 19, 2012
Related Publication 20170365546A1 · Dec 21, 2017