Vertical transistor with air-gap spacer
A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.
1. A vertical transistor comprising:
a fin or nanowire extending upward from a surface of a semiconductor substrate;
a gate electrode located entirely adjacent to each sidewall of the fin or nanowire;
a bottom source/drain contact adjacent to the gate electrode;
a dielectric spacer disposed between the gate electrode and the bottom source/drain contact, wherein the dielectric spacer comprises a vertical air-gap embedded in a dielectric material;
a bottom source/drain region having a topmost surface directly contacting a bottommost surface of the fin or nanowire; and
a top source/drain region having a bottommost surface directly contacting a topmost surface of the fin or nanowire.
2. The vertical transistor of claim 1 , further comprising a bottom spacer located beneath the gate electrode and on a surface of a topmost semiconductor layer of the semiconductor substrate.
3. The vertical transistor of claim 2 , wherein the dielectric spacer further comprises a horizontal air-gap embedded in the dielectric material, wherein the horizontal air-gap of the dielectric spacer is located below a bottommost surface of the the bottom spacer.
4. The vertical transistor of claim 3 , wherein the horizontal air-gap of the dielectric spacer is interconnected with the vertical air-gap of the dielectric spacer.
5. The vertical transistor of claim 1 , wherein the vertical air-gap of the dielectric spacer has a topmost surface that is located below a topmost surface of the gate electrode.
6. The vertical transistor of claim 5 , wherein the vertical air-gap height is 30 to 95% of a height of the gate electrode.
7. The vertical transistor of claim 1 , wherein a distance between the gate electrode and the bottom source/drain contact is from 4 nm to 20 nm.
8. The vertical transistor of claim 1 , wherein the vertical air-gap height is from 15 nm to 50 nm and the vertical air-gap width is from 4 nm to 20 nm.
9. The vertical transistor of claim 1 , further comprising a conformal dielectric layer that is in contact with an exposed surface of each of the gate electrode and the bottom source/drain contact.
10. The vertical transistor of claim 1 , wherein the dielectric material of the dielectric spacer is selected from the group consisting of amorphous carbon, a carbon-doped oxide, a fluorine-doped oxide, SiCOH and SiBCN.
11. The vertical transistor of claim 1 , wherein the top source/drain region has sidewalls that are vertically aligned with the sidewalls of the fin or nanowire.
12. The vertical transistor of claim 1 , wherein the dielectric spacer further comprises a horizontal air-gap embedded in the dielectric and located between the gate electrode and the semiconductor substrate.
13. The vertical transistor of claim 12 , wherein the horizontal air-gap height is from 4 nm to 20 nm and the horizontal air-gap width is from 30 nm to 50 nm.
14. The vertical transistor of claim 12 , wherein the horizontal air-gap and the vertical air-gap are interconnected.
15. The vertical transistor of claim 1 , wherein the dielectric spacer is in contact with a sidewall of the top source/drain region and extends above a topmost surface of the top source/drain region.
16. The vertical transistor of claim 15 , further comprising a top source/drain contact located above the top source/drain region, wherein the dielectric spacer is located between the gate electrode and the top source/drain contact.