Semiconductor structure with inverted U-shaped cap layer
View Patent ↗The present invention provides a semiconductor structure, the semiconductor structure comprises a substrate having a dielectric layer disposed thereon, a gate conductive layer disposed on the substrate and disposed in the dielectric layer, two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and a cap layer overlying the top surface and two sidewalls of the gate conductive layer, wherein parts of the cap layer are located right above the two spacers.
1. A semiconductor structure, comprising:
a substrate having a dielectric layer disposed thereon; and
a first gate structure, disposed in the dielectric layer, wherein the first gate structure comprises:
a gate conductive layer, disposed on the substrate and disposed in the dielectric layer;
two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer; a cap layer, covering on the gate conductive layer and the two spacers, wherein a portion of the cap layer is disposed right above the two spacers; and
a high-k layer and a work function metal layer, wherein a top surface of the high-k layer and a top surface of the work function metal layer are higher than the top surface of each spacer; and
two contact etch stop layers, disposed on an outer sidewall of the two spacers respectively, wherein the cap layer is not disposed right above each contact etch stop layer.
2. The semiconductor structure of claim 1 , further comprising at least one void disposed in the cap layer, wherein the at least one void is lower than the top surface of the gate conductive layer.
3. The semiconductor structure of claim 1 , wherein the cap layer provides a first stress to a channel region of the first gate structure.
4. The semiconductor structure of claim 3 , further comprising a second gate structure, the second gate structure comprises a second cap layer, the second cap layer provides a second stress to a channel region of the second gate structure, wherein the first stress is different from the second stress.
5. The semiconductor structure of claim 1 , wherein a top surface of each contact etch stop layer is higher than the top surfaces of the two spacers.
6. The semiconductor structure of claim 1 , wherein a top surface of each contact etch stop layer is higher than the top surface of the gate conductive layer.
7. The semiconductor structure of claim 1 , wherein a top surface of each contact etch stop layer is lower than the top surface of the gate conductive layer.
8. The semiconductor structure of claim 1 , wherein the top surface of the gate conductive layer is a flat top surface.
9. The semiconductor structure of claim 1 , wherein a height of each one of the two spacers is lower than half of a height of the gate conductive layer.
10. A semiconductor structure, comprising:
a substrate having a dielectric layer disposed thereon; and
a first gate structure, disposed in the dielectric layer, wherein the first gate structure comprises:
a gate conductive layer, disposed on the substrate and disposed in the dielectric layer;
two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer;
a cap layer, covering on the gate conductive layer and the two spacers, wherein a portion of the cap layer is disposed right above the two spacers; and
at least one void disposed in the cap layer, wherein the at least one void is lower than the top surface of the gate conductive layer.
11. The semiconductor structure of claim 10 , wherein the cap layer provides a first stress to a channel region of the first gate structure.
12. The semiconductor structure of claim 11 , further comprising a second gate structure, the second gate structure comprises a second cap layer, the second cap layer provides a second stress to a channel region of the second gate structure, wherein the first stress is different from the second stress.
13. The semiconductor structure of claim 10 , further comprising a high-k layer and a work function metal layer, wherein a top surface of the high-k layer and a top surface of the work function metal layer are higher than the top surface of the spacer.
14. The semiconductor structure of claim 10 , further comprising two contact etch stop layers, disposed on an outer sidewall of the two spacers respectively.
15. The semiconductor structure of claim 14 , wherein a top surface of each contact etch stop layer is higher than the top surfaces of the two spacers.
16. The semiconductor structure of claim 14 , wherein the cap layer is not disposed right above each contact etch stop layer.
17. The semiconductor structure of claim 14 , wherein a top surface of each contact etch stop layer is higher than the top surface of the gate conductive layer.
18. The semiconductor structure of claim 14 , wherein a top surface of each contact etch stop layer is lower than the top surface of the gate conductive layer.
19. The semiconductor structure of claim 10 , wherein the top surface of the gate conductive layer is a flat top surface.
20. The semiconductor structure of claim 10 , wherein a height of each one of the two spacers is lower than half of a height of the gate conductive layer.